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成本降低 70–90% 相較於原級晶圓
100mm – 300mm 所有直徑
100nm – 2μm SiO₂ 氧化塗層選項
大量折扣 數量計價
線上訂購 — 在我們的 商店
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虛擬片與機械晶圓

虛擬片與機械級矽晶圓是半導體晶圓分級中成本最低的矽基板 — 以最寬鬆的規格製造,且僅供非生產用途。其唯一目的是佔據實體空間並在製程設備中提供熱/機械存在感,而無需承擔電性或表面品質的要求。

這些晶圓係由無法達到原級或測試級規格的 CZ 矽晶棒段製成 — 通常是晶棒尾端與錐端、規格外的電阻率材料,或因外觀或尺寸原因而在原級檢測中被淘汰的晶圓。這些材料並非報廢或回收,而是被再利用為具成本效益的虛擬晶圓,相較於將原級材料用於爐管填充與機台設定,每年可為晶圓廠節省數百萬美元。

在 GINECHIP,我們供應所有標準直徑(100mm–300mm)的虛擬片與機械晶圓,表面處理範圍從研磨態(霧面)到單面拋光。氧化塗層選項 — 100nm 至 2μm 的熱 SiO₂ — 可保護矽表面免受凹坑與污染吸附,將使用壽命延長至多個熱循環。LPCVD 氮化矽塗層則為高溫氧化環境提供額外保護。我們提供極具競爭力的大量價格:訂購越多,單片成本越低。

虛擬晶圓應用

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Furnace Fill & Thermal Uniformity

Horizontal and vertical diffusion/LPCVD furnaces require full boat-loading for proper gas flow dynamics and temperature uniformity. Dummy wafers fill vacant slots at the ends of each boat (end-caps) and between production lots, maintaining consistent thermal mass and gas residence time. A single vertical furnace may use 60–120 dummy wafers continuously.

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Tool Setup & Chamber Conditioning

New etch, deposition, or implant chambers require tens to hundreds of wafers for initial conditioning — coating chamber walls, stabilizing RF plasma impedance, and seasoning shields and clamps before production wafers are committed. Using dummy wafers for this task avoids wasting costly prime or monitor-grade material.

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Temperature Profiling & Thermal Uniformity

Thermocouple-instrumented dummy wafers map temperature distribution across furnace boats and RTP chambers. Multiple thermal profiling runs with TC wafers characterize ramp rates, overshoot, and steady-state uniformity before production qualification begins.

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Mechanical Handling Qualification

Automated material handling systems (AMHS), wafer sorters, EFEMs, and load-lock robots require testing with physical wafers to verify alignment, gripping force, mapping sensors, and wafer-centering accuracy. Dummy wafers allow extensive handling trials with zero risk to product material.

氧化虛擬晶圓

裸矽虛擬晶圓的操作壽命有限:在氧化性或反應性製程環境中經過 1–2 次熱循環後,矽表面會產生凹坑、粗糙化與污染吸附,可能生成微粒並污染製程腔體。對於需要更長虛擬晶圓壽命的晶圓廠,氧化虛擬晶圓提供保護性 SiO₂ 阻障層,可承受多次熱循環才需更換。

氧化層作為犧牲性阻障層 — 它會隨每次爐管循環逐漸增厚並劣化,但可保護底層矽免受凹坑與重金屬污染吸附。當氧化層最終變得太厚(> 3μm)、太粗糙,或污染超過可接受限值時,只需以全新的氧化虛擬晶圓替換,成本僅為原級晶圓的一小部分。

氧化層厚度可用熱循環次數最適用於
100nm SiO₂ 1–2 thermal cycles Short furnace seasoning, single-use
200nm SiO₂ 3–5 thermal cycles Standard weekly furnace fill rotation
500nm SiO₂ 8–12 thermal cycles Extended campaigns, reduced replacement frequency
1μm SiO₂ 15–25 thermal cycles Long-life dummy wafers, monthly replacement
2μm SiO₂ 30–50+ thermal cycles Maximum lifetime, minimum cost-per-cycle

對於使用含氯化學品進行嚴苛製程(例如 HCl 吸雜循環、TCA 爐管清洗)的晶圓廠,LPCVD 氮化矽塗層虛擬晶圓(100nm 或 200nm Si₃N₄)可提供優異的抗化學性。氮化矽塗層晶圓在含 HCl 環境中可承受多達 100 次熱循環,是經常進行原位清洗的爐管的首選。

表面處理選項

研磨態(霧面)

最低成本的表面處理。晶圓表面維持切割/研磨後的狀態,呈霧面、不反光的外觀。適用於表面品質無關緊要的爐管端蓋與機械搬運測試。單片成本最低 — 非常適合高消耗量的應用。

成本:最低 用途:爐管填充

單面拋光(SSP)

單面拋光至鏡面光潔度。當虛擬晶圓必須緊密模擬生產晶圓的熱發射率與氣流交互作用時,此為必要條件。用於 RTP 與磊晶反應器的機台設定。

成本:中等 用途:RTP/磊晶設定

大量訂購與數量折扣

虛擬晶圓是大量消耗性商品。單一座 300mm 晶圓廠每月可能消耗 2,000–5,000 片虛擬晶圓,用於爐管填充、腔體調節與機台設定。GINECHIP 的供應鏈以大宗供貨為架構 — 您每月的數量承諾越高,單片價格就越低。典型的價格級距適用於每月 500、2,500 與 10,000+ 片。

對於消耗模式可預測的晶圓廠,我們提供附每月排定交貨的一攬子採購協議,免除反覆詢價的需求並確保供應一致。虛擬晶圓與其他基板類型(原級、測試級、SOI)的合併出貨,可享有額外的運費最佳化與整合文件。

技術規格

參數可用範圍/數值
Wafer Type Dummy Grade, Mechanical Grade (non-production, lowest cost)
Growth Method CZ (Czochralski) — recycled ingot tail/cone ends accepted
Diameter 100mm, 125mm, 150mm, 200mm, 300mm (all diameters)
Dopant Type Any — P-type or N-type, no guarantee of consistent type lot-to-lot
Resistivity Range Any — loose/no specification (lowest-cost sourcing)
Crystal Orientation 〈100〉 or 〈111〉 — as available, not selected
Thickness Per SEMI M1–M13, wide tolerance (±20μm or greater)
TTV (Total Thickness Variation) ≤ 10μm (200mm), ≤ 15μm (300mm)
Bow / Warp ≤ 50μm Bow, ≤ 60μm Warp (all diameters, as-sawn tolerance)
Surface Finish As-lapped (matte), etched (chemical), or single-side polished (SSP)
Oxide Coating (Thermal SiO₂) 100nm, 200nm, 500nm, 1μm, 2μm (for extended thermal cycling)
Nitride Coating (LPCVD Si₃N₄) 100nm, 200nm (high-temperature oxidation/diffusion barrier)
Edge Profile As-sawn or SEMI standard round/T-edge if polished
Flat / Notch May or may not conform to SEMI — as available
Particle Specification None — visual inspection for gross contamination only
Laser Mark Optional — batch-level marking only (no individual wafer traceability)
Backside Treatment As-lapped or etched — no additional treatment required
Packaging Bulk cassette, multi-wafer pack, or plastic shippers — cost-optimized
Cost vs. Prime 70–90% cost reduction vs. equivalent prime-grade wafers

品質與檢驗

雖然虛擬晶圓不受適用於原級與測試級材料的完整計量檢驗,GINECHIP 仍執行最低限度的檢測協議,以確保晶圓可安全搬運且不會損壞客戶設備。

Mechanical Dimensions Thickness, diameter, and flat/notch geometry verified against SEMI standard tolerances with relaxed acceptance windows. Ensures compatibility with automated wafer handling equipment.
Visual Inspection High-intensity collimated light inspection for edge chips, cracks, and gross surface contamination. Wafers with damage capable of generating particles or causing handling failures are rejected.
Oxide Thickness (if coated) Ellipsometry or reflectometry for oxide/nitride-coated dummy wafers. 9-point thickness map documents coating uniformity (±5% for thermal oxide, ±8% for LPCVD nitride).
Cassette / Packaging Integrity Cassette and shipper inspection to verify freedom from cracks, particulate contamination, and electrostatic discharge (ESD) hazards. Bulk packaging must protect wafers during transit.
Batch-Level Lot Traceability Each shipment includes a packing list with lot origin, diameter, thickness, surface finish, and coating type (if applicable). Individual wafer traceability is not provided for dummy-grade material.

需要虛擬片或機械晶圓嗎?

請指定您所需的直徑、表面處理、氧化塗層厚度(如適用)、每月數量與目標價位 — 我們的供應鏈團隊將在 24 小時內取得具競爭力的報價。每月承諾 500+ 片可享數量折扣。

ISO 9001:2015 大量折扣 氧化/氮化物選項 節省 70–90% 成本