先進封裝 — 2.5D、3D-IC、FOWLP、RDL、TSV基板 | GINECHIP

2.5D · 3D-IC · FOWLP封裝架構

L/S 0.4/0.4μm最小RDL間距

TSV · TGV · μ-Bump關鍵封裝技術

TB/s/mm互連頻寬

概述

先進封裝技術是半導體產業超越摩爾定律的關鍵路徑。GINECHIP提供完整的先進封裝基板和製程服務，涵蓋2.5D矽中介層、3D-IC堆疊、扇出型晶圓級封裝（FOWLP）和TSV技術，支援從晶片級到系統級的異質整合需求。

我們提供業界領先的品質和精度，所有製程均在ISO Class 5無塵室環境下運行，確保最高的可靠性和良率。

封裝技術

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Interposer: 300mm Si, 100μm thickTSV: 10μm dia, 100μm deep, AR 10:1RDL: Cu damascene, 2–5 layersL/S: 0.4/0.4μm minimumμ-bump pitch: 40–55μmC4 bump pitch: 130–150μm

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Stack height: 2–12 dieμ-bump pitch: 10–40μmHybrid bond pitch: < 1μm (R&D)TSV: 5μm dia, 50μm deepWafer thinning: < 50μmTemp: TCB or mass reflow

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Die shift: < 2μmRDL: Cu, 2–5 layers, L/S 2/2μmMold compound: EMCBall pitch: 300–500μmPackage thickness: < 0.5mmWafer: 200mm or 300mm recon

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RDL L/S: 1/1μm (Cu damascene)Dielectric: polyimide or SiO₂Multi-die integrationPassive integration (IPD)Shielding: Cu backside metalWafer: 300mm

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Laminate: BT, ABF, or corelessDie thickness: 50–100μmMicrovia: 30–60μm diaL/S: 8/8μm (mSAP)Embedded passives possiblePanel-level processing option

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Glass: borosilicate, fused silicaTGV: 20–50μm dia, AR 6:1Metallization: Cu-filled TGVCTE: 3–8 ppm/K (tunable)Panel: up to 510×515mmLoss tangent: < 0.005 @ 10GHz

可用製程服務

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主要應用領域

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RDL設計規則

參數	標準RDL（≤ 10μm L/S）	精細線路RDL（≤ 5μm L/S）	超精細RDL（≤ 2μm L/S）
Minimum L/S	5/5μm	2/2μm	0.4/0.4μm
Cu Thickness	5–8μm	3–5μm	1–3μm
Via Diameter	20–30μm	10–15μm	5–10μm
Dielectric	Polyimide (PID)	Polyimide or BCB	SiO₂ (CVD)
Dielectric Constant (k)	3.0–3.5	2.6–3.0	3.9 (SiO₂)
Number of Layers	1–3	2–5	2–8
Cu Deposition Method	Semi-additive (SAP)	SAP or Damascene	Cu Damascene
Planarization	None or CMP	CMP	CMP (per layer)

基板選擇

先進封裝的基板選擇對於整體封裝性能至關重要。我們的工程團隊將根據您的封裝架構、熱預算和電氣性能要求，推薦最適合的基板材料和規格組合。

品質與計量

品質描述

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ISO 9001:2015 JEDEC Standards TSV · RDL · Bump 3D Integration