矽晶圓基板
MEMS、CMOS、功率器件和光子學的基礎材料。根據您的精確電阻率、晶向和表面規格進行工程設計。
概述
矽晶圓仍是半導體元件製造的主要基板 — 佔全球半導體基板市場90%以上。在GINECHIP，我們採購和經銷各種主要等級、直徑和規格的矽基板，服務50多個國家的晶圓廠、MEMS代工廠、研發機構和封裝廠。
無論您的應用需要用於量產CMOS的Prime級CZ晶圓、用於功率元件的超平坦FZ晶圓、用於RF-SOI開關的SOI基板，還是用於製程驗證的經濟型測試級晶圓 — 我們的供應鏈以完整的材料追溯性提供一致的批次品質。
Silicon Wafer Product Categories
Select a category to explore detailed specifications, manufacturing methods, and request a quotation.
Prime Silicon Wafers
Device-grade CZ & FZ substrates. Sub-nanometer roughness, tight resistivity and thickness tolerances for CMOS, MEMS, and power devices.
Test / Monitor Wafers
Cost-optimized wafers for fab equipment qualification, process monitoring, and daily tool checks. Consistent electrical and mechanical properties.
Dummy / Mechanical Wafers
Lowest-cost non-production wafers for furnace fill, tool setup, thermal uniformity control, and mechanical handling qualification.
Reclaimed Wafers
Chemically-mechanically stripped and repolished wafers restored to near-prime quality. 30–60% cost savings with up to 5 reclaim cycles.
Ultra-Thin / Taiko Wafers
Wafers thinned to 20μm with Taiko ring process for 3D-IC stacking, power devices, BSI sensors, and advanced packaging.
FZ High-Resistivity Wafers
Float Zone silicon with >10 kΩ·cm resistivity and extreme purity. O₂/C < 5×10¹⁵. Preferred substrate for RFICs, photonics, and radiation detectors.
SOI Wafers
Silicon-on-Insulator substrates with device layer on buried oxide. Smart Cut, BESOI, SIMOX, ELTRAN. For RF-SOI, FD-SOI, MEMS, photonics.
Thermal Oxide on Silicon
High-quality thermally-grown SiO₂ layers 10nm–4μm. Dry, wet, and pyrogenic oxidation for gate oxides, diffusion masks, and etch-stop layers.
Nitride on Silicon (Si₃N₄)
LPCVD & PECVD Si₃N₄ films 20nm–2μm. Stoichiometric and low-stress formulations. Diffusion barrier, passivation, MEMS hard mask.
Silicon Epi Wafers
CVD homoepitaxial Si on Si. Custom doping and thickness 0.5–200μm. For CMOS sensors, power MOSFETs, IGBTs, and BiCMOS.
晶體生長方法
我們供應通過以下錠生長技術生產的基板：
CZ（柴氏法）
最常見的方法 — 在受控熱條件下從熔融矽中拉出單晶種子。以具競爭力的成本生產200mm和300mm晶圓，適用於大量製造。
FZ（浮區法）
通過區域熔煉精煉的超高純度矽。極低的氧和碳含量。對於高壓IGBT、RF功率晶體管和輻射檢測器至關重要。
MCZ（磁場柴氏法）
在CZ生長過程中施加磁場抑制熔體對流，減少氧摻入並改善電阻率均勻性。首選用於CCD/CMOS圖像傳感器和高階類比IC。
技術規格
| 參數 | 可用範圍 / 值 |
|---|---|
| Diameter | 100mm (4″), 150mm (6″), 200mm (8″), 300mm (12″) |
| Type / Dopant | P-type (Boron), N-type (Phosphorus, Arsenic, Antimony) |
| Resistivity | 0.001–10,000 Ω·cm (custom ranges available) |
| Orientation | 〈100〉, 〈111〉, 〈110〉 (off-cut angles available) |
| Thickness | 200μm–1000μm (standard SEMI specs ± custom) |
| Polish | SSP (Single-Side), DSP (Double-Side), CMP-finished |
| Backside | Bright-etched, Lapped, Polysilicon, Oxide/Nitride layer |
| TTV / Bow / Warp | As low as < 2μm TTV, < 5μm Bow, < 10μm Warp |
| Particles | ≤ 10 particles @ 0.2μm (Class 1 cleanroom packaging) |
表面處理與背面處理
正面拋光
- CMP (Chemical-Mechanical Polish) — sub-nanometer RMS roughness for advanced lithography
- SSP (Single-Side Polished) — standard for most MEMS and CMOS processes
- DSP (Double-Side Polished) — required for double-side alignment photolithography
- Epi-Ready — surface prepared for epitaxial growth with < 5Å native oxide
背面選項
- Bright-Etched — acid-etched for uniform appearance
- Lapped — mechanically ground for thickness control
- Polysilicon Backseal — gettering layer for heavy-metal contamination control
- Thermal Oxide / LPCVD Nitride — dielectric backside for etch-stop or isolation
- Custom Backside Film Stacks — oxide-nitride, ONO, or metal backside
應用
品質與認證
每個批次出貨均附有合格證書，包括電阻率圖、厚度輪廓(TTV/Bow/Warp)、顆粒計數和晶體學驗證。我們的供應鏈在ISO 9001:2015認證的品質管理體系下運作，具有完整的SEMI標準追溯性。