Thermal Oxide on Silicon
Silicon wafers with high-quality thermally-grown SiO₂ layers from 10nm to 4μm. Dry, wet, and pyrogenic oxidation processes for gate oxides, diffusion masks, etch-stop layers, and MEMS sacrificial layers. Tight uniformity control with wafer-scale ellipsometry mapping included.
What Is Thermal Oxide on Silicon?
Thermal silicon dioxide (SiO₂) is the cornerstone dielectric of silicon semiconductor technology — a high-quality, stoichiometric oxide film grown directly on single-crystal silicon by exposing the wafer to an oxidizing ambient at elevated temperatures (800–1200°C). Unlike deposited oxides, thermally grown SiO₂ consumes the underlying silicon, producing a pristine Si/SiO₂ interface with exceptionally low interface trap density (Dit < 10¹⁰ cm⁻²eV⁻¹). This irreplaceable interface quality has kept thermal SiO₂ at the heart of MOSFET gate stacks for over 50 years, even as high-κ dielectrics have supplemented it in advanced nodes.
GINECHIP supplies thermal oxide wafers produced through all three established oxidation chemistries — dry (O₂), wet (H₂O vapor), and pyrogenic (H₂/O₂ combustion) — each offering distinct trade-offs in growth rate, film density, and electrical quality. Thicknesses from 10nm (gate-quality dry oxide) to 4μm (field oxide and MEMS sacrificial layers) are routinely produced with ±1% within-wafer uniformity, verified by spectroscopic ellipsometry mapping at 49 or 81 points per wafer.
Every thermal oxide wafer lot is shipped with a comprehensive Certificate of Analysis (CoA) including 49-point or 81-point ellipsometry thickness map, refractive index uniformity, C-V (capacitance–voltage) measurements for oxide charge and interface trap density, and AFM surface roughness scans. ISO 9001:2015 certified partner facilities ensure process control traceable to NIST standards.
Thermal Oxidation Processes Compared
The choice of oxidation chemistry determines film density, growth rate, electrical quality, and hydrogen content — factors that directly impact device performance and process throughput. The table below summarizes the key differences between the three primary thermal oxidation methods.
| Parameter | Dry Oxidation (O₂) | Wet Oxidation (H₂O Vapor) | Pyrogenic (H₂/O₂ Torch) |
|---|---|---|---|
| Oxidant Species | O₂ (molecular oxygen) | H₂O (water vapor) | H₂O from H₂ + O₂ reaction |
| Typical Temperature | 850–1100°C | 900–1100°C | 800–1050°C |
| Growth Rate (1000°C) | ~8–15 nm/hr (100nm film) | ~60–100 nm/hr (100nm film) | ~50–90 nm/hr (100nm film) |
| Film Density | 2.27 g/cm³ (highest) | 2.20 g/cm³ (slightly lower) | 2.24 g/cm³ (high) |
| Refractive Index | 1.462 ± 0.002 | 1.458 ± 0.003 | 1.460 ± 0.002 |
| Dielectric Strength | >12 MV/cm | >10 MV/cm | >11 MV/cm |
| Interface Quality (Dit) | 5×10⁹ – 2×10¹⁰ cm⁻²eV⁻¹ | 1×10¹⁰ – 5×10¹⁰ cm⁻²eV⁻¹ | 8×10⁹ – 3×10¹⁰ cm⁻²eV⁻¹ |
| Fixed Oxide Charge (Qf) | 5×10¹⁰ – 2×10¹¹ cm⁻² | 1×10¹¹ – 5×10¹¹ cm⁻² | 8×10¹⁰ – 3×10¹¹ cm⁻² |
| Hydrogen Content | Very low (no H₂O used) | Moderate (incorporated as Si–OH) | Low–Moderate |
| Etch Rate (5:1 BHF) | ~90 nm/min | ~110 nm/min | ~100 nm/min |
| Film Stress (compressive) | –250 to –400 MPa | –200 to –350 MPa | –220 to –380 MPa |
| Best For | Gate oxide, tunnel oxide | Field oxide, sacrificial layers | High-throughput gate/field oxide |
Thermal SiO₂/Si Material Stack
High-quality thermally-grown silicon dioxide. Dense (2.27 g/cm³ dry), low pinhole density, excellent dielectric strength (>10 MV/cm), and high chemical resistance.
Atomically abrupt interface with sub-oxide transition region (SiOx, x<2). Interface trap density Dit as low as 5×10⁹ cm⁻²eV⁻¹ for dry oxide after forming gas anneal.
Single-crystal silicon substrate. Available in all standard diameters, orientations, doping types (n-type/p-type), and resistivity ranges. Approximately 44% of the final oxide thickness is consumed from the silicon surface during growth.
The Deal–Grove Oxidation Kinetics
Thermal oxidation of silicon follows the Deal–Grove model, which describes oxide growth as a competition between oxidant diffusion through the existing oxide and the chemical reaction at the Si/SiO₂ interface. For thin oxides (< 50nm), the process is reaction-rate-limited and growth is linear with time; for thick oxides (> 200nm), it becomes diffusion-limited and growth follows a parabolic rate law.
The linear-parabolic model is expressed as: x²o + Axo = B(t + τ), where xo is oxide thickness, B/A is the linear rate constant, B is the parabolic rate constant, and τ accounts for any initial native oxide. Both rate constants follow Arrhenius temperature dependence with activation energies of ~2.0 eV (linear) and ~1.2 eV (parabolic). This model has guided oxidation process engineering for over five decades and remains the foundation for thermal SiO₂ process design at GINECHIP.
Applications & Market Segments
Gate Oxide (MOSFET)
Ultra-thin thermal SiO₂ (2–20nm) as the critical gate dielectric in planar CMOS, power MOSFETs, and IGBTs. Carrier mobility at the Si/SiO₂ interface directly determines transistor drive current and switching performance.
Diffusion Mask
Patterned thermal oxide blocks dopant diffusion during source/drain and well formation. Selectivity of >1000:1 for B, P, As in SiO₂ vs. Si at 900–1100°C. Fundamental to all planar silicon processing.
Etch-Stop & Release Layer
Thermal SiO₂ serves as a precise etch-stop for Si DRIE and as a sacrificial release layer in MEMS surface micromachining. HF selectivity against silicon enables clean structural release.
MEMS Sacrificial Oxide
Thick thermal oxides (0.5–4μm) as sacrificial layers in polysilicon surface micromachining for accelerometers, gyroscopes, pressure sensors, and micro-mirror arrays.
Hard Mask for Etching
SiO₂ hard masks for deep silicon etching (DRIE Bosch process). Etch selectivity of >100:1 Si:SiO₂ in SF₆/C₄F₈ plasmas enables high-aspect-ratio structures exceeding 50:1.
SOI Buried Oxide (BOX)
Thermal oxide as the insulating BOX layer in Bonded SOI (BESOI) and Smart Cut SOI technologies. Provides electrical isolation, radiation hardness, and latch-up immunity for RF-SOI and FD-SOI.
Field Oxide (LOCOS/STI)
Thick thermal oxide (300–800nm) for inter-device isolation. LOCOS (Local Oxidation of Silicon) and STI (Shallow Trench Isolation) liner oxides define active areas and prevent parasitic channel formation.
Optical Waveguide Cladding
Thermal SiO₂ lower cladding for silicon photonic waveguides. Low optical loss (<0.1 dB/cm at 1550nm) and high-index contrast with the Si core enable compact photonic integrated circuits.
Technical Specifications
| Parameter | Available Range / Values |
|---|---|
| SiO₂ Thickness Range | 10nm – 4μm (standard); up to 6μm on request |
| Thickness Uniformity | ±1% within-wafer (Std Dev), ±2% wafer-to-wafer |
| Refractive Index (n) | 1.46 ± 0.01 at 632.8nm (stoichiometric thermal SiO₂) |
| Dielectric Breakdown Strength | >10 MV/cm (gate-quality dry oxide, 25°C) |
| Wafer Diameters | 100mm (4″), 150mm (6″), 200mm (8″), 300mm (12″) |
| Wafer Orientations | 〈100〉, 〈111〉, 〈110〉 (〈100〉 recommended for gate oxide) |
| Oxidation Methods | Dry (O₂), Wet (H₂O vapor), Pyrogenic (H₂/O₂ torch) |
| Film Stress | –200 to –400 MPa compressive (as-grown), adjustable via anneal |
| Etch Rate (5:1 BHF) | ~100nm/min thermally grown; ~150nm/min deposited |
| Surface Roughness (RMS) | < 0.2nm on Si/SiO₂ interface, < 0.5nm on SiO₂ surface |
| Ellipsometry Mapping | 49-point and 81-point wafer maps with contour and 3D plots |
Metrology & Quality Assurance
Thermal oxide wafer quality is verified through a multi-technique metrology protocol at every lot. Each shipment includes a full Certificate of Analysis with quantitative data for all measured parameters.
Ready to Specify Your Thermal Oxide Wafers?
Tell us your target SiO₂ thickness, oxidation method (dry/wet/pyrogenic), wafer diameter, doping type, and quantity — our oxide process engineers will provide a detailed quotation with metrology specifications and lead time within 24 hours.