TEOS Oxide Silicon Wafers

50nm – 10μm Thickness Range

Within-Wafer ±2% Within-Wafer Uniformity

RI 1.46 @ 633nm Refractive Index (RI)

Stress < 100 MPa Film Stress

Product Overview

GINECHIP provides TEOS Oxide Silicon Wafers with SiO₂ films deposited by TEOS PECVD (350–400°C) or TEOS LPCVD (700–720°C). Designed for tight control of thickness, dielectric performance, and production-ready surface quality (RMS roughness < 0.5 nm).

Available on prime CZ Si (100) or (111) for 100mm–300mm wafers. The SiO₂ thickness spans 50 nm–10 μm with ±5% tolerance, while refractive index remains stable at 1.46 ± 0.005 @ 633 nm—helpful for optical stack consistency and metrology correlation.

Key advantage: tunable stress with excellent thickness control and low roughness—ideal for MEMS and IMD stacks.

Deposition Methods

Choose the process window that matches your thermal budget and conformality requirement. GINECHIP supports TEOS SiO₂ by PECVD and LPCVD TEOS with stress engineering and robust metrology correlations.

Low Temp

PECVD TEOS

PECVD TEOS (Low-Temperature Plasma-Enhanced)

Temperature 350–400°C

Deposition Rate 50–200 nm/min

Stress Range -200 to +100 MPa

Conformality Good (> 80%)

Plasma-Enhanced Chemical Vapor Deposition using TEOS precursor at 350–400°C. Plasma energy dissociates the precursor molecules, enabling deposition at significantly lower temperatures than thermal CVD. Produces films with excellent step coverage, conformality, and controllable stress (compressive or tensile). The industry standard for inter-metal dielectrics, passivation layers, and MEMS sacrificial layers where thermal budget constraints preclude high-temperature processing.

High Density

LPCVD TEOS

LPCVD TEOS (High-Density Hot-Wall Furnace)

Temperature 700–720°C

Deposition Rate 10–50 nm/min

Stress Range -300 to 0 MPa

Conformality Excellent (> 95%)

Low-Pressure Chemical Vapor Deposition using TEOS at 700–720°C in a hot-wall furnace. Operates in the surface-reaction-limited regime, yielding exceptional within-wafer and wafer-to-wafer uniformity. Produces films with higher density, lower wet etch rates, and superior electrical properties compared to PECVD films. Ideal for hard masks, gate spacers, and applications requiring maximum film quality where thermal budget allows.

Key Properties

Achieve stable optical and electrical performance with n = 1.46 ± 0.005 @ 633 nm. The TEOS SiO₂ film provides dielectric strength > 8 MV/cm and breakdown voltage > 400 V / 1 μm, supporting reliable insulation for IMD, gate-spacing layers, and passivation applications.

Control film quality with thickness 50 nm–10 μm (±5%) and wafer uniformity of ±2% (200 mm) / ±3% (300 mm). Stress is tuneable <100 MPa (compressive/tensile; PECVD −200~+100 MPa, LPCVD −300~0 MPa). Etch-rate at 6:1 BOE is PECVD 20–80 nm/min / LPCVD 10–30 nm/min, with RMS roughness < 0.5 nm for clean interfaces.

Quality & Metrology

Each shipment is supported by batch-level metrology records to help you verify incoming film performance. Key metrics include thickness (±5%), refractive index 1.46 ± 0.005 @633 nm, uniformity ±2% (200 mm) / ±3% (300 mm), inter-wafer repeatability ±3%, stress (<100 MPa), and RMS roughness < 0.5 nm.

TEOS oxide silicon wafers are vacuum sealed in Class 100 cleanroom packing to minimize contamination risk. The sealed format supports stable handling through storage and line-to-line transfer for MEMS sacrifice layers, IMD, and photonic/etch hard-mask workflows.

Customization & Ordering

Select the wafer stack to match your process needs: prime CZ Si substrates in 100–300 mm, available as SSP/DSP and (100)/(111) orientations. Choose TEOS SiO₂ deposition options via TEOS PECVD (350–400°C) or LPCVD TEOS (700–720°C) with film thickness 50 nm–10 μm (±5%) and stress tuned <100 MPa (PECVD −200~+100 MPa; LPCVD −300~0 MPa).

Lead time and order quantities are confirmed based on your requested size, thickness, stress target, and deposition method (PECVD 350–400°C or LPCVD 700–720°C). For production planning, GINECHIP will advise feasibility and minimum order quantity when quoting your exact configuration.

Technical Specifications

Parameter	Specification / Values
Base Substrate	Prime CZ Si, 100mm–300mm, SSP/DSP, (100) or (111)
Coating Material	SiO₂ via TEOS PECVD
Deposition Method	PECVD (350–400°C), LPCVD TEOS (700–720°C) option
Thickness Range	50nm–10μm, ±5% tolerance
Refractive Index	1.46 ± 0.005 @ 633nm
Within-Wafer Uniformity	±2% for 200mm, ±3% for 300mm
Wafer-to-Wafer Repeatability	±3%
Stress	Compressive or tensile, tunable; < 100 MPa as-deposited
Etch Rate in 6:1 BOE	PECVD: ~20–80 nm/min; LPCVD: ~10–30 nm/min
Dielectric Strength	> 8 MV/cm
Breakdown Voltage	> 400V for 1μm film
Surface Roughness	RMS < 0.5nm
Film Density	2.1–2.2 g/cm³
FTIR Signature	Si-O-Si stretching at 1080 cm⁻¹
Packaging	Vacuum-sealed, single wafer cassette, Class 100 cleanroom

Applications

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MEMS Sacrificial Layers

TEOS PECVD oxide is the dominant sacrificial material in surface micromachining. Its high etch rate in HF vapor or BOE relative to thermal oxide and silicon nitride enables precise release of suspended microstructures — accelerometer proof masses, gyroscope combs, pressure sensor diaphragms, and micro-mirror hinges — without attacking structural layers.

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Inter-Metal Dielectrics (IMD)

PECVD TEOS films serve as the primary dielectric between consecutive metal layers in multi-level interconnect stacks. Low deposition temperature preserves underlying aluminum or copper metallization, while excellent gap-fill properties prevent void formation in high-aspect-ratio trenches at sub-micron pitches.

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Hard Masks for Deep Etching

LPCVD TEOS films provide dense, pinhole-free hard mask layers for deep reactive ion etching (DRIE) of silicon. The low etch rate in fluorine-based chemistries (10–30 nm/min in 6:1 BOE) relative to photoresist enables high-selectivity pattern transfer for through-silicon vias (TSVs) and deep MEMS structures exceeding 300μm depth.

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Optical Waveguides

TEOS SiO₂ films with precisely controlled refractive index (1.46 ± 0.005) and thickness uniformity (±2%) form the core and cladding layers in planar lightwave circuits (PLCs), arrayed waveguide gratings (AWGs), and silicon photonic interposers. Low optical loss and compatibility with CMOS foundry processes make TEOS the material of choice.

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Gate Spacers & Sidewall Passivation

LPCVD TEOS is widely used to form self-aligned gate spacers in CMOS transistor fabrication. The highly conformal deposition coats vertical sidewalls uniformly, defining the lightly-doped drain (LDD) and source/drain implant offset regions critical for short-channel effect control at advanced nodes.

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Passivation & Encapsulation

PECVD TEOS oxide combined with silicon nitride forms robust, multi-layer passivation stacks that protect finished ICs from moisture ingress, mobile ion contamination, and mechanical damage. Stress-engineered films prevent die cracking during dicing and packaging while maintaining hermetic sealing.

Metrology & Quality Control

Built for tight process control with ellipsometry thickness, FTIR confirmation, and stress monitoring (Stoney formula). Surface and film quality are verified using AFM, along with wet etch calibration (6:1 BOE), Mercury probe CV/IV, and OES online plasma monitoring. Particle cleanliness is checked via KLA-Tencor particle inspection (Class 100).

Spectroscopic Ellipsometry Primary metrology for film thickness and refractive index. Multi-angle (55°, 65°, 75°) measurements at 633nm wavelength across 49-point wafer maps. Thickness accuracy ±0.5nm, refractive index precision ±0.002.

FTIR Spectroscopy Fourier Transform Infrared spectroscopy identifies the characteristic Si-O-Si stretching peak at 1080 cm⁻¹ and Si-OH hydroxyl content at 3400–3650 cm⁻¹. Confirms stoichiometric oxide composition and quantifies hydrogen/water incorporation that affects etch rate and dielectric properties.

Wafer Curvature / Stress Measurement Laser-scanning or interferometric measurement of wafer bow before and after deposition. Stress calculated via Stoney equation; tunable from -300 MPa (compressive) to +100 MPa (tensile) through RF power and pressure adjustments during PECVD.

AFM Surface Roughness Atomic force microscopy over 1×1μm and 10×10μm scan areas. RMS roughness consistently < 0.5nm for both PECVD and LPCVD films, ensuring compatibility with subsequent photolithography and bonding steps.

Wet Etch Rate Calibration Etch rate measured in 6:1 buffered oxide etch (BOE) at 25°C. PECVD: 20–80 nm/min; LPCVD: 10–30 nm/min. Etch rate ratio vs thermal oxide provides a direct proxy for film density and impurity incorporation.

Mercury Probe CV / IV Mercury-probe capacitance-voltage (CV) and current-voltage (IV) measurements on MOS capacitor test structures. Dielectric strength > 8 MV/cm, breakdown voltage > 400V per micron of film thickness.

Optical Emission Spectroscopy (OES) In-situ plasma monitoring during PECVD deposition for real-time process control. Tracks Si, O, and contaminant emission lines to ensure consistent film stoichiometry and detect chamber conditioning drift.

Particle Inspection KLA-Tencor Surfscan surface particle scan at 0.2μm threshold per SEMI M53. Post-deposition particle adders ≤ 5 for Class 100 cleanroom processing.

Get Started Today

Talk to GINECHIP to source TEOS Oxide Silicon Wafers that match your film stack, thickness target, and metrology needs.

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