TEOS Oxide on Silicon Substrates
High-quality TEOS (Tetraethyl Orthosilicate) PECVD oxide films on silicon wafers for MEMS sacrificial layers, inter-metal dielectrics, hard masks, and optical waveguides.
TEOS PECVD Oxide Films on Silicon
TEOS (Tetraethyl Orthosilicate) oxide films deposited via PECVD represent the most widely used silicon dioxide thin-film technology in semiconductor and MEMS manufacturing. Unlike thermal oxidation — which consumes silicon from the substrate — TEOS PECVD deposits SiO₂ onto the wafer surface, enabling oxide formation on any substrate material, over existing device features, and at temperatures compatible with aluminum metallization (350–400°C).
The TEOS molecule (Si(OC₂H₅)₄) serves as a liquid precursor that decomposes in an RF plasma to produce high-purity, stoichiometric SiO₂ with conformal step coverage and excellent uniformity. By tuning RF power, pressure, temperature, and gas flow ratios, the film properties — stress, density, wet etch rate, refractive index, and hydrogen content — can be precisely engineered to match application requirements.
At GINECHIP, we provide TEOS oxide films deposited onto customer-specified silicon substrates from 100mm to 300mm diameter, with thicknesses ranging from 50nm to 10μm and within-wafer uniformity of ±2%. Both PECVD (350–400°C) and LPCVD TEOS (700–720°C) processes are available. Every wafer ships with a Certificate of Analysis including ellipsometry thickness maps, refractive index, film stress, and FTIR spectra.
Deposition Methods: PECVD vs LPCVD TEOS
Two TEOS-based deposition routes exist, each with distinct advantages. The choice between PECVD and LPCVD TEOS depends primarily on the substrate's thermal budget and the required film quality.
PECVD TEOS
Plasma-enhanced at 350–400°C — low thermal budget
Plasma-Enhanced Chemical Vapor Deposition using TEOS precursor at 350–400°C. Plasma energy dissociates the precursor molecules, enabling deposition at significantly lower temperatures than thermal CVD. Produces films with excellent step coverage, conformality, and controllable stress (compressive or tensile). The industry standard for inter-metal dielectrics, passivation layers, and MEMS sacrificial layers where thermal budget constraints preclude high-temperature processing.
LPCVD TEOS
Low-pressure thermal at 700–720°C — maximum film quality
Low-Pressure Chemical Vapor Deposition using TEOS at 700–720°C in a hot-wall furnace. Operates in the surface-reaction-limited regime, yielding exceptional within-wafer and wafer-to-wafer uniformity. Produces films with higher density, lower wet etch rates, and superior electrical properties compared to PECVD films. Ideal for hard masks, gate spacers, and applications requiring maximum film quality where thermal budget allows.
MEMS Sacrificial Layer Applications
TEOS PECVD oxide is the sacrificial material of choice in surface micromachining — the dominant MEMS fabrication technology used to produce inertial sensors, RF MEMS switches, micro-mirrors, and microfluidic devices. The sacrificial layer is deposited and patterned beneath a structural material (typically polysilicon), then selectively etched away to release the freely-moving mechanical structure.
Key advantages of TEOS oxide in this role include: (1) high etch selectivity in HF-based chemistries — TEOS etches 10–100× faster than thermal oxide, enabling rapid release without attacking structural silicon; (2) low deposition temperature (350–400°C) that preserves underlying CMOS circuits in integrated MEMS+ASIC processes; (3) tunable stress to prevent structural layer buckling or cracking after release; and (4) excellent thickness uniformity (±2%) that ensures consistent sacrificial gap height across the entire wafer — critical for capacitive sensors where gap determines sensitivity.
Optical Waveguide Applications
TEOS SiO₂ films with precisely controlled refractive index (1.46 ± 0.005) and sub-nanometer surface roughness are the core building blocks of planar lightwave circuits (PLCs). In a typical waveguide stack, a doped TEOS layer with slightly higher refractive index serves as the waveguide core, surrounded by undoped TEOS cladding layers with lower index. The high index contrast enables tight optical confinement with bend radii below 500μm — essential for dense photonic integration at the chip scale.
For arrayed waveguide gratings (AWGs) used in wavelength-division multiplexing (WDM) systems, TEOS films must maintain ±2% thickness uniformity across full 200mm or 300mm wafers to achieve the sub-nanometer optical path-length precision required for 100GHz and 50GHz channel spacing in telecom networks.
Deposition Process & Quality Control
Our TEOS deposition process begins with a liquid TEOS source (≥ 99.9999% purity) delivered via a temperature-controlled vaporizer into the PECVD chamber. The wafer sits on a heated chuck (350–400°C) while RF plasma (13.56 MHz or dual-frequency) dissociates the TEOS and O₂ precursors. Helium carrier gas improves plasma stability and uniformity. For LPCVD TEOS, wafers are loaded vertically into a hot-wall furnace tube (700–720°C) in a low-pressure environment (200–400 mTorr), where thermal decomposition drives surface-reaction-limited deposition for maximum conformality.
Post-deposition annealing (400–450°C in N₂ or forming gas for 30–60 minutes) is available to densify PECVD films, reduce hydrogen content, and stabilize stress — particularly important for MEMS release where uncontrolled stress relaxation can cause device failure after weeks or months of shelf storage.
Technical Specifications
| Parameter | Available Range / Values |
|---|---|
| Base Substrate | Prime CZ Si, 100mm–300mm, SSP/DSP, (100) or (111) |
| Coating Material | SiO₂ via TEOS PECVD |
| Deposition Method | PECVD (350–400°C), LPCVD TEOS (700–720°C) option |
| Thickness Range | 50nm–10μm, ±5% tolerance |
| Refractive Index | 1.46 ± 0.005 @ 633nm |
| Within-Wafer Uniformity | ±2% for 200mm, ±3% for 300mm |
| Wafer-to-Wafer Repeatability | ±3% |
| Stress | Compressive or tensile, tunable; < 100 MPa as-deposited |
| Etch Rate in 6:1 BOE | PECVD: ~20–80 nm/min; LPCVD: ~10–30 nm/min |
| Dielectric Strength | > 8 MV/cm |
| Breakdown Voltage | > 400V for 1μm film |
| Surface Roughness | RMS < 0.5nm |
| Film Density | 2.1–2.2 g/cm³ |
| FTIR Signature | Si-O-Si stretching at 1080 cm⁻¹ |
| Packaging | Vacuum-sealed, single wafer cassette, Class 100 cleanroom |
Applications & Market Segments
MEMS Sacrificial Layers
TEOS PECVD oxide is the dominant sacrificial material in surface micromachining. Its high etch rate in HF vapor or BOE relative to thermal oxide and silicon nitride enables precise release of suspended microstructures — accelerometer proof masses, gyroscope combs, pressure sensor diaphragms, and micro-mirror hinges — without attacking structural layers.
Inter-Metal Dielectrics (IMD)
PECVD TEOS films serve as the primary dielectric between consecutive metal layers in multi-level interconnect stacks. Low deposition temperature preserves underlying aluminum or copper metallization, while excellent gap-fill properties prevent void formation in high-aspect-ratio trenches at sub-micron pitches.
Hard Masks for Deep Etching
LPCVD TEOS films provide dense, pinhole-free hard mask layers for deep reactive ion etching (DRIE) of silicon. The low etch rate in fluorine-based chemistries (10–30 nm/min in 6:1 BOE) relative to photoresist enables high-selectivity pattern transfer for through-silicon vias (TSVs) and deep MEMS structures exceeding 300μm depth.
Optical Waveguides
TEOS SiO₂ films with precisely controlled refractive index (1.46 ± 0.005) and thickness uniformity (±2%) form the core and cladding layers in planar lightwave circuits (PLCs), arrayed waveguide gratings (AWGs), and silicon photonic interposers. Low optical loss and compatibility with CMOS foundry processes make TEOS the material of choice.
Gate Spacers & Sidewall Passivation
LPCVD TEOS is widely used to form self-aligned gate spacers in CMOS transistor fabrication. The highly conformal deposition coats vertical sidewalls uniformly, defining the lightly-doped drain (LDD) and source/drain implant offset regions critical for short-channel effect control at advanced nodes.
Passivation & Encapsulation
PECVD TEOS oxide combined with silicon nitride forms robust, multi-layer passivation stacks that protect finished ICs from moisture ingress, mobile ion contamination, and mechanical damage. Stress-engineered films prevent die cracking during dicing and packaging while maintaining hermetic sealing.
Metrology & Quality Assurance
Every TEOS oxide wafer lot is characterized through a comprehensive, multi-technique metrology protocol at ISO 9001:2015 certified facilities. A Certificate of Analysis (CoA) documenting all measured parameters is provided with each shipment.
Need TEOS Oxide Coated Wafers?
Specify your substrate diameter, TEOS film thickness, deposition method (PECVD or LPCVD), stress target, and quantity — our coating specialists will provide a detailed quotation with metrology data and lead time within 24 hours.