Custom Process Development Workflow

A structured, phase-gate approach to developing customer-specific reclaim protocols. We begin with a detailed technical consultation to understand your wafer type, film stack, substrate material, device integration requirements, and quality targets. This is followed by analytical characterization of representative wafers (XRR, ellipsometry, FTIR) to identify film composition, thickness, and interface properties. A tailored etch sequence is designed based on selectivity data, then tested on witness or low-value wafers before full-lot qualification.

Film Stack Analysis & Characterization

Before any reclaim process can be designed, the existing film stack must be thoroughly characterized. We use a multi-technique approach: spectroscopic ellipsometry for film thickness and optical constants (n,k), X-ray reflectivity (XRR) for ultra-thin film thickness, density, and interface roughness, Fourier-transform infrared spectroscopy (FTIR) for chemical bond identification (SiO₂, Si₃N₄, SiC, low-κ dielectrics, polymers), and energy-dispersive X-ray spectroscopy (EDS) for elemental composition of metal films. The complete film stack map — layer order, thickness, composition, and interface quality — drives the reclaim chemistry selection.

Etch Selectivity Matrix & Optimization

The core of any reclaim protocol is the etch selectivity matrix: which etchants remove the target film(s) at an acceptable rate while minimizing attack on the underlying substrate and any layers that must be preserved. We compile selectivity data (etch rate ratio of target film to substrate) for each candidate chemistry across relevant process conditions (temperature, concentration, agitation). Multi-film stacks add complexity: the etchant for Film 2 must not damage the substrate after Film 1 has been removed. DOE (Design of Experiments) methods are employed to optimize multi-step etch sequences for minimum substrate loss and maximum throughput.

Multi-Film Stack Stripping

Real-world process wafers rarely carry a single film — they carry stacks of 3–10 different materials deposited in sequence. Each film requires a specific removal chemistry, and the order of removal must be carefully engineered to prevent cross-reactions, galvanic corrosion, and undercut attack on underlying films. A typical reclaim protocol for a CMOS test wafer might sequence: O₂ plasma ash (photoresist) → wet metal etch (Al/TiN/Ti) → hot H₃PO₄ (Si₃N₄) → HF-based (SiO₂) → silicon etch-back (KOH/TMAH) → RCA clean → CMP polish.

Exotic Substrate Handling

Custom reclaim protocols for non-silicon substrates require specialized chemistries, process conditions, and handling procedures. SiC and GaN substrates demand high-temperature, aggressive chemistries (molten KOH, hot H₃PO₄/H₂SO₄) for which standard silicon reclaim tooling is inadequate. InP and GaAs substrates are attacked by chemistries safe for silicon (HF etches InP; alkaline solutions etch GaAs), requiring completely different etch strategies. Sapphire substrates are chemically inert to most wet etchants, demanding mechanical or plasma-based approaches. Our exotic substrate protocols are developed with dedicated tooling to prevent cross-contamination with silicon processing.

Case Study: GaN-on-SiC HEMT Wafer Reclaim

Challenge: A customer producing GaN HEMT devices on semi-insulating 4H-SiC substrates needed a reclaim process for wafers that failed electrical test after epitaxial growth and gate formation. The SiC substrate cost alone exceeded $800 per 100mm wafer, making reuse economically critical. However, the AlGaN/GaN epitaxial layers are highly resistant to wet chemical etching (near-zero etch rate in standard silicon chemistries), and aggressive etchants that remove GaN (molten KOH, reactive ion etching) also attack the SiC substrate — limiting the number of reclaim cycles.

Solution: After exhaustive etch selectivity screening, we developed a two-step dry + wet process: (1) ICP-RIE using Cl₂/BCl₃ chemistry to remove the GaN and AlGaN epitaxial layers with high selectivity to the AlN nucleation layer, which serves as a natural etch stop; (2) wet chemical removal of the AlN layer using AZ400K developer at 80°C, which etches AlN at ~50 nm/min with negligible SiC attack (< 1nm/min). Post-reclaim CMP restores the SiC surface to epi-ready condition. The protocol achieved 3 reclaim cycles with < 5μm cumulative SiC loss per cycle, delivering > $2,000 substrate cost savings per wafer over the full reclaim life.

Case Study: Multi-Layer MEMS Process Wafer Reclaim

Challenge: A MEMS foundry needed to reclaim monitor wafers from their sacrificial-layer release process, which left a complex stack of PECVD SiO₂ (2μm), LPCVD Si₃N₄ (0.3μm), poly-Si (0.5μm), and Ti/Pt metallization on 150mm silicon wafers. The Pt layer was particularly problematic: Pt is noble and near-immune to all standard wet etchants, and Pt contamination in subsequent reclaim runs would cause severe metallic contamination of other wafers processed in the same wet benches.

Solution: We designed a sequence that removed Pt first — using a dedicated wet bench to prevent cross-contamination — via hot aqua regia (HCl/HNO₃ at 3:1, 80°C), which dissolves Pt through formation of chloroplatinic acid (H₂PtCl₆). The Ti adhesion layer was removed in dilute HF. Subsequent steps followed a more standard sequence: BOE (SiO₂), hot H₃PO₄ (Si₃N₄), TMAH (poly-Si). The Pt removal step was segregated on dedicated tooling with rigorous TXRF verification of zero Pt carryover to other work-in-progress. The protocol reclaimed wafers to monitor-grade specifications at 35% of new wafer cost, achieving payback on development costs within the first 200 wafers processed.