Material Customization
Tailor your semiconductor substrate material properties — resistivity, doping profile, crystal orientation, thickness, and surface finish — to match your exact device requirements.
Overview
Standard off-the-shelf wafers serve many applications, but breakthrough devices often require precisely tailored material properties that cannot be met by catalog specifications. Our material customization service lets you define the exact resistivity range, doping profile, crystal orientation, thickness, and surface condition needed for your device physics — then we source or fabricate wafers to those specifications.
We deliver industry-leading quality and precision.
Resistivity Customization
Resistivity Description
| Parameter | Available Range / Values |
|---|---|
| Resistivity Range | 0.001–10,000 Ω·cm (custom narrow bands available) |
| Tolerance | ±5% standard, ±2% tight, ±1% ultra-tight |
| Radial Uniformity | ≤ 3% variation (4PP, 49-point map) |
| P-type Dopants | Boron (B) — 0.001–10,000 Ω·cm |
| N-type Dopants | Phosphorus (P), Arsenic (As), Antimony (Sb) |
| Intrinsic / High-Res | > 1,000 Ω·cm (FZ, neutron-transmutation doped) |
| Heavily Doped | < 0.005 Ω·cm (N+ Sb, P+ B for epi substrates) |
| Measurement Method | 4-point probe, eddy current, Hall effect per SEMI MF84 |
Resistivity Paragraph 2
Doping Profile Engineering
Doping Description
P-Type (Boron-Doped)
Silicon wafers doped with boron for positive carrier (hole) conduction. Available with precisely controlled resistivity from heavily doped to near-intrinsic, with tight tolerance across the full wafer surface.
N-Type (Phosphorus/Antimony)
Silicon wafers doped with phosphorus or antimony for negative carrier (electron) conduction. Higher electron mobility compared to P-type for superior high-frequency device performance.
Intrinsic / High-Resistivity
Ultra-high resistivity silicon (> 10 kΩ·cm) for RF substrates, photodetectors, and radiation sensors. Minimal free carrier absorption for low-loss high-frequency applications. Achieved through float-zone refining or precise compensation doping.
Crystal Orientation Selection
Orientation Description
| Parameter | Available Range / Values |
|---|---|
| Standard Orientations | 〈100〉, 〈111〉, 〈110〉 |
| Off-Cut / Vicinal | 0.5°–6.0° toward 〈110〉, 〈111〉, or 〈211〉 |
| Tolerance | ±0.1° standard, ±0.05° precision |
| Flat Alignment | SEMI M1 primary/secondary flat or notch |
| Wafer ID Laser Mark | SEMI T7 OCR-compatible, alphanumeric, dot-matrix |
H 100Title
H 111Title
Orientation Paragraph 2
Thickness Customization
Thickness Description
| Parameter | Available Range / Values |
|---|---|
| Standard Range | 200μm–1000μm |
| Ultra-Thin | 100μm–200μm (ground + stress-relieved) |
| TTV (Total Thickness Variation) | < 2μm standard, < 1μm tight |
| Bow | < 30μm standard, < 10μm tight |
| Warp | < 40μm standard, < 15μm tight |
| Surface Roughness (Ra) | < 0.5nm CMP, < 5nm DSP, < 50nm lapped |
Thickness Paragraph 2
Surface Finish Options
Surface Finish Description
CMP Polished
Chemical-mechanical planarization. Single-side or double-side polished wafers with sub-nanometer surface roughness for epitaxial growth and direct wafer bonding.
- Ra < 0.5nm (AFM, 10×10μm scan)
- Haze < 0.2 ppm (SP1/Tencor)
- Available single-side or double-side
Single-Side Polished (SSP)
Front-side polished to device-grade finish (< 0.5nm Ra), back-side etched or lapped. Cost-effective option for applications where only the device side requires optical-quality surface.
- Front: CMP (Ra < 0.5nm)
- Back: bright-etched or lapped
- SEMI M1 compliant
Double-Side Polished (DSP)
Both sides polished to high-quality finish. Required for MEMS fabrication with through-wafer features, optical applications, and wafer bonding requiring both surfaces to be pristine.
- Both sides Ra < 0.5nm
- Improved wafer flatness
- 200mm and 300mm available
Epi-Ready Finish
Ultra-clean, particle-free surface optimized for epitaxial growth. Native oxide controlled to < 1nm. HF-last or ozone-last clean process available. Shipped in nitrogen-purged packaging.
- Native oxide < 5Å (ellipsometry)
- COP-free for high-quality epi
- N₂-purged packaging
Lapped / As-Cut
Economical finish for bulk mechanical applications, thermal test wafers, and process development where optical-grade surface is not required. Surface roughness typically 0.2–0.5μm Ra.
- Ra 0.5–5.0μm
- Fast delivery
- Bulk pricing available
Backside Treatments
Backside Description
Gettering Title
Dielectric Backside Title
Special Material Grades
Special Description
Backside Oxide / Poly-Silicon
Thermal oxide or deposited poly-silicon layer on wafer backside for gettering of metallic impurities during high-temperature processing. Essential for maintaining bulk lifetime in power devices.
Bulk Micro Defect (BMD) Engineering
Controlled oxygen precipitation to create internal gettering sites for metallic impurities. BMD density and denuded zone depth tailored to your thermal budget and device architecture requirements.
Crystal Originated Particle (COP) Control
COP-free or COP-reduced silicon wafers for defect-sensitive applications. Achieved through optimized crystal growth parameters and post-growth annealing. Critical for gate oxide integrity in advanced CMOS and flash memory.
Applications
Quality & Certification
Every custom wafer lot is accompanied by a comprehensive Certificate of Analysis including: 4-point probe resistivity map (full wafer), doping concentration verification (SIMS or SRP), crystal orientation verification (XRD), thickness map, surface roughness measurement (AFM or optical profilometry), and particle count (per IEST-STD-CC1246).
Quality Paragraph 2
Need Custom Material Specifications for Your Device?
Tell us your required resistivity, doping, orientation, thickness, and surface finish — and we'll provide a detailed quotation within 24 hours.