Material Customization
Tailor your semiconductor substrate material properties — resistivity, doping profile, crystal orientation, thickness, and surface finish — to match your exact device requirements.
Overview
Standard off-the-shelf wafers serve many applications, but breakthrough devices often require precisely tailored material properties that cannot be met by catalog specifications. Our material customization service lets you define the exact resistivity range, doping profile, crystal orientation, thickness, and surface condition needed for your device physics — then we source or fabricate wafers to those specifications.
Every custom order is backed by ISO 9001-certified fabrication and full material qualification — SIMS or four-point probe verification of resistivity and doping, X-ray diffraction for crystal orientation, and a certificate of conformance shipped with every lot.
Resistivity Customization
Resistivity is the most fundamental electrical property of a semiconductor substrate, dictating carrier concentration and device behavior. We offer precise resistivity targeting across the full spectrum — from heavily doped (sub-0.005 Ω·cm) for low-resistance ohmic contacts to ultra-high resistivity (>10,000 Ω·cm) for RF and photonics applications — with every wafer lot verified by 49-point full-wafer 4-point probe mapping.
| Parameter | Available Range / Values |
|---|---|
| Resistivity Range | 0.001–10,000 Ω·cm (custom narrow bands available) |
| Tolerance | ±5% standard, ±2% tight, ±1% ultra-tight |
| Radial Uniformity | ≤ 3% variation (4PP, 49-point map) |
| P-type Dopants | Boron (B) — 0.001–10,000 Ω·cm |
| N-type Dopants | Phosphorus (P), Arsenic (As), Antimony (Sb) |
| Intrinsic / High-Res | > 1,000 Ω·cm (FZ, neutron-transmutation doped) |
| Heavily Doped | < 0.005 Ω·cm (N+ Sb, P+ B for epi substrates) |
| Measurement Method | 4-point probe, eddy current, Hall effect per SEMI MF84 |
For applications requiring extremely tight resistivity windows — such as power MOSFET drift regions, IGBT buffer layers, or precision analog circuits — we supply wafers with ±1% ultra-tight tolerance and radial uniformity better than 2%. Neutron transmutation doping (NTD) is our preferred method for the most demanding high-resistivity applications where doping homogeneity at the atomic level is non-negotiable.
Doping Profile Engineering
Beyond bulk resistivity, the doping profile — including dopant species, concentration gradient, and axial uniformity — determines carrier mobility, lifetime, and junction characteristics. Select from boron (B), phosphorus (P), arsenic (As), or antimony (Sb) dopants, each offering distinct diffusion behavior and electrical activation properties for your specific thermal budget and device architecture.
P-Type (Boron-Doped)
Silicon wafers doped with boron for positive carrier (hole) conduction. Available with precisely controlled resistivity from heavily doped to near-intrinsic, with tight tolerance across the full wafer surface.
N-Type (Phosphorus/Antimony)
Silicon wafers doped with phosphorus or antimony for negative carrier (electron) conduction. Higher electron mobility compared to P-type for superior high-frequency device performance.
Intrinsic / High-Resistivity
Ultra-high resistivity silicon (> 10 kΩ·cm) for RF substrates, photodetectors, and radiation sensors. Minimal free carrier absorption for low-loss high-frequency applications. Achieved through float-zone refining or precise compensation doping.
Crystal Orientation Selection
Crystal orientation impacts anisotropic etching behavior, carrier mobility, oxide growth rate, and interface trap density. Select the orientation that optimizes your device — whether it is the industry-standard 〈100〉 for CMOS logic and VLSI, 〈111〉 for MEMS bulk micromachining and power devices, or 〈110〉 for high hole mobility in advanced transistor channels.
| Parameter | Available Range / Values |
|---|---|
| Standard Orientations | 〈100〉, 〈111〉, 〈110〉 |
| Off-Cut / Vicinal | 0.5°–6.0° toward 〈110〉, 〈111〉, or 〈211〉 |
| Tolerance | ±0.1° standard, ±0.05° precision |
| Flat Alignment | SEMI M1 primary/secondary flat or notch |
| Wafer ID Laser Mark | SEMI T7 OCR-compatible, alphanumeric, dot-matrix |
〈100〉 Orientation — CMOS & VLSI Standard
- Lowest interface trap density (Dit) with thermal SiO2
- Industry standard for CMOS logic, DRAM, NAND flash
- Optimal for anisotropic wet etching (KOH, TMAH)
- Compatible with all major foundry processes
〈111〉 Orientation — MEMS & Power Devices
- Slowest etch rate in alkaline solutions — ideal for etch-stop layers
- Preferred for bulk micromachined MEMS (pressure sensors, accelerometers)
- Higher atomic density for epitaxial growth of III-V layers
- Common for IGBT, thyristor, and power diode substrates
For heteroepitaxial growth of III-V materials on silicon or specialized MEMS structures, off-cut (vicinal) wafers are available with controlled miscut angles from 0.5° to 6.0° to promote step-flow growth and suppress anti-phase domain formation. Custom off-cut direction and angle combinations can be specified for your epitaxial process window.
Thickness Customization
Wafer thickness directly influences mechanical strength, thermal mass, RF performance, and die handling yield. We supply wafers from ultra-thin 100μm for 3D IC stacking and flexible electronics to standard 725μm for high-volume CMOS manufacturing, with tight total thickness variation (TTV) control ensuring uniform processing across the entire wafer surface.
| Parameter | Available Range / Values |
|---|---|
| Standard Range | 200μm–1000μm |
| Ultra-Thin | 100μm–200μm (ground + stress-relieved) |
| TTV (Total Thickness Variation) | < 2μm standard, < 1μm tight |
| Bow | < 30μm standard, < 10μm tight |
| Warp | < 40μm standard, < 15μm tight |
| Surface Roughness (Ra) | < 0.5nm CMP, < 5nm DSP, < 50nm lapped |
Ultra-thin wafers (< 200μm) are processed with stress-relief grinding and polishing to minimize subsurface damage and warp. For applications requiring extreme flatness — such as nanoimprint lithography templates or wafer bonding — TTV as low as < 1μm is achievable. All thickness parameters are verified by non-contact capacitance gauging with full-wafer mapping.
Surface Finish Options
Surface finish determines epitaxial growth quality, wafer bonding strength, particle adhesion, and lithography resolution. Choose from five distinct finish grades — each optimized for specific downstream processing requirements. All wafers are cleaned and inspected to ISO Class 4 cleanroom standards prior to packaging.
CMP Polished
Chemical-mechanical planarization. Single-side or double-side polished wafers with sub-nanometer surface roughness for epitaxial growth and direct wafer bonding.
- Ra < 0.5nm (AFM, 10×10μm scan)
- Haze < 0.2 ppm (SP1/Tencor)
- Available single-side or double-side
Single-Side Polished (SSP)
Front-side polished to device-grade finish (< 0.5nm Ra), back-side etched or lapped. Cost-effective option for applications where only the device side requires optical-quality surface.
- Front: CMP (Ra < 0.5nm)
- Back: bright-etched or lapped
- SEMI M1 compliant
Double-Side Polished (DSP)
Both sides polished to high-quality finish. Required for MEMS fabrication with through-wafer features, optical applications, and wafer bonding requiring both surfaces to be pristine.
- Both sides Ra < 0.5nm
- Improved wafer flatness
- 200mm and 300mm available
Epi-Ready Finish
Ultra-clean, particle-free surface optimized for epitaxial growth. Native oxide controlled to < 1nm. HF-last or ozone-last clean process available. Shipped in nitrogen-purged packaging.
- Native oxide < 5Å (ellipsometry)
- COP-free for high-quality epi
- N₂-purged packaging
Lapped / As-Cut
Economical finish for bulk mechanical applications, thermal test wafers, and process development where optical-grade surface is not required. Surface roughness typically 0.2–0.5μm Ra.
- Ra 0.5–5.0μm
- Fast delivery
- Bulk pricing available
Backside Treatments
The wafer backside plays a critical role in device performance — from gettering metallic impurities during thermal processing to providing electrical contact for vertical power devices. Engineered backside treatments enhance yield, improve carrier lifetime, and enable advanced packaging integration.
Gettering — Metallic Contaminant Control
- Intrinsic Gettering (IG): BMD-engineered oxygen precipitates for internal trapping
- Poly-Silicon Backside: CVD poly-Si layer with high grain-boundary density
- Phosphorus Diffusion: P-doped backside layer for heavy-metal gettering
- Backside Damage: Controlled mechanical damage (sandblast, grooving) for extrinsic gettering
Dielectric Backside — Isolation & Passivation
- Thermal SiO₂: 100nm–2μm for electrical isolation in SOI-like structures
- LPCVD Si₃N₄: Diffusion barrier and passivation layer
- PECVD SiO₂/Si₃N₄ stacks: Low-temperature dielectric for post-CMOS processing
- ALD Al₂O₃/HfO₂: High-κ dielectrics for advanced device isolation
Special Material Grades
Beyond standard doping and surface specifications, advanced device architectures often require engineered bulk material properties. Our special material grades address oxygen precipitation behavior, crystal defect density, and sub-surface damage — parameters that directly impact device yield and reliability in high-volume manufacturing.
Backside Oxide / Poly-Silicon
Thermal oxide or deposited poly-silicon layer on wafer backside for gettering of metallic impurities during high-temperature processing. Essential for maintaining bulk lifetime in power devices.
Bulk Micro Defect (BMD) Engineering
Controlled oxygen precipitation to create internal gettering sites for metallic impurities. BMD density and denuded zone depth tailored to your thermal budget and device architecture requirements.
Crystal Originated Particle (COP) Control
COP-free or COP-reduced silicon wafers for defect-sensitive applications. Achieved through optimized crystal growth parameters and post-growth annealing. Critical for gate oxide integrity in advanced CMOS and flash memory.
Applications
Quality & Certification
Every custom wafer lot is accompanied by a comprehensive Certificate of Analysis including: 4-point probe resistivity map (full wafer), doping concentration verification (SIMS or SRP), crystal orientation verification (XRD), thickness map, surface roughness measurement (AFM or optical profilometry), and particle count (per IEST-STD-CC1246).
Our quality management system is certified to ISO 9001:2015 and operates in full compliance with SEMI M1–M83 standards. Every process — from crystal growth through final inspection — is traceable to your purchase order and lot number. We retain split samples from every production lot for 5 years to support root-cause analysis and continuous improvement.
Need Custom Material Specifications for Your Device?
Tell us your required resistivity, doping, orientation, thickness, and surface finish — and we'll provide a detailed quotation within 24 hours.