Ion Implantation & Doping
Precision ion implantation and thermal diffusion doping for semiconductor device fabrication. B, P, As, Sb dopants with controlled concentration profiles on silicon, SOI, and compound semiconductor substrates.
Overview
Ion implantation is the dominant doping technology in semiconductor manufacturing, offering precise control over dopant concentration, depth, and spatial distribution that diffusion alone cannot achieve. By accelerating ionized dopant atoms (B⁺, P⁺, As⁺, Sb⁺, In⁺) to energies from 5 keV to 3 MeV and scanning them across the wafer, we create precisely engineered doping profiles — from shallow source/drain extensions (< 20nm junction depth) to deep retrograde wells (> 3μm).
Our implant services cover the complete process chain: pre-implant surface preparation (screen oxide growth), ion implantation with beam current optimization for each species, post-implant annealing (RTA spike or furnace soak), and electrical characterization (sheet resistance mapping, SIMS, Hall measurement). We process silicon wafers from 100mm to 200mm, including SOI, epitaxial, and double-side polished substrates.
Dopant Species & Capabilities
Boron — P-Type Dopant
The primary <strong>p-type dopant</strong> for silicon. Available as atomic B⁺ for shallow junctions (< 50nm) or molecular BF₂⁺ for pre-amorphization and enhanced activation at lower thermal budgets. Boron is used for source/drain extensions, halo implants, channel doping, and well formation. Typical as-implanted peak concentration: 1×10¹⁸ – 5×10²⁰ cm⁻³.
Phosphorus — N-Type Dopant
The workhorse <strong>n-type dopant</strong> for wells, source/drain, and emitter formation. Available as P⁺ (singly charged) and P²⁺ (doubly charged for higher effective energy). Phosphorus is the preferred n-type species for deep wells and buried layers due to its high solubility (up to 1×10²¹ cm⁻³) and moderate diffusivity. Typical activation > 95% after 950°C RTA.
Arsenic — Heavy N-Type Dopant
The <strong>heavy n-type dopant</strong> of choice for shallow junctions and high-concentration source/drain regions. Arsenic's high atomic mass yields very tight as-implanted profiles with minimal straggle — ideal for ultra-shallow junctions (< 20nm) in advanced CMOS. Peak concentration can exceed 1×10²¹ cm⁻³ with spike RTA activation at 1000–1100°C.
Antimony & Indium — Low-Diffusivity Dopants
<strong>Antimony (Sb⁺)</strong> is an n-type dopant with ~10× lower diffusivity than phosphorus — ideal for retrograde wells and buried layers that must maintain profile integrity. <strong>Indium (In⁺)</strong> is a p-type dopant with ~10× lower diffusivity than boron, used for retrograde p-wells and punch-through stoppers. Both species are typically implanted at moderate doses and activated with RTA at 1000–1100°C.
Implant Parameter Control
| Parameter | Range / Specification | Control Mechanism |
|---|---|---|
| Implant Angle (Tilt) | 0° – 10° (typically 7° to suppress channeling) | Electrostatic beam steering ±0.1° |
| Wafer Twist | 0° – 360° (typically 22°–45° with 7° tilt) | Mechanical platen rotation ±0.5° |
| Beam Current | 10 μA – 10 mA (species and energy dependent) | Faraday cup feedback ±1% |
| Dose Uniformity | < 1% 1σ across 200mm wafer | Dual mechanical scan (slow horizontal, fast vertical) |
| Wafer Temperature | Ambient – 500°C (heated implant option) | Platen temperature control, IR pyrometer |
| Charge Neutralization | Low-energy electron flood gun for insulating substrates | Plasma bridge or electron shower, < 10V surface potential |
| Channeling Suppression | Screen oxide (10–50nm SiO₂) + 7° tilt | Amorphized surface layer via pre-amorphization implant (PAI) |
| Vacuum | < 5×10⁻⁷ Torr (end station) | Cryopump + turbomolecular pump stack |
All parameters are independently programmable per implant step. Multi-step implant sequences (chain implants) with different energies, doses, and angles are supported within a single wafer run.
Post-Implant Annealing
Rapid Thermal Annealing (RTA)
<strong>Rapid thermal annealing</strong> provides the time-temperature profile needed for dopant activation while minimizing diffusion. Spike anneals (< 1s at peak temperature) preserve ultra-shallow junction profiles and achieve > 90% electrical activation. Soak anneals (10–120s) are used for defect annealing and implant damage recovery. Temperature uniformity ±2°C across 200mm wafers.
Furnace Annealing
<strong>Conventional furnace annealing</strong> for high-thermal-budget processes and batch processing. Used for deep well drive-in (2–4 hours at 1000–1100°C) and oxidation-anneal combined steps. Batch size 25–50 wafers per run for cost-effective volume processing.
Dopant Activation Verification
<strong>Comprehensive electrical and chemical verification</strong> of implant and anneal results. Four-point probe 49-point sheet resistance mapping provides within-wafer uniformity data. SIMS profiling with 1×10¹⁴ cm⁻³ detection limit verifies chemical dopant distribution. Hall effect measurement determines carrier concentration and mobility. Spreading resistance profiling (SRP) offers 5nm depth resolution for junction depth (Xⱼ) measurement.
Process Flow
Wafer Preparation
RCA clean, screen oxide growth (10–50nm thermal SiO₂), wafer inspection and lot traceability.
Ion Implantation
Species selection, energy/dose programming, 7° tilt angle for channeling suppression, dual-scan implant with real-time beam current monitoring.
Post-Implant Clean
Photoresist strip (if used as implant mask), RCA clean to remove surface contamination, optional screen oxide strip in dilute HF.
Post-Implant Annealing
RTA spike anneal (900–1100°C, < 1s dwell) for dopant activation with minimal diffusion, or furnace anneal (700–1100°C, 10 min – 4 hr) for deep drive-in. N₂, Ar, or forming gas ambient.
Electrical Characterization
49-point 4-point probe sheet resistance mapping, junction depth verification by SIMS or SRP, Hall effect measurement for carrier concentration and mobility.
Final Inspection & Shipment
Optical inspection, Certificate of Conformance with sheet resistance map, lot traceability documentation, cleanroom packaging in wafer shippers or single-wafer cases.
Channeling Suppression
When an ion travels along a major crystallographic axis, it can channel deep into the lattice, creating an unpredictable tail in the doping profile. We employ multiple strategies to suppress channeling: wafer tilt of 7° (or other angles per customer specification), screen oxide growth (10–50nm SiO₂), and pre-amorphization implant (PAI) using Si⁺ or Ge⁺ at high dose to create an amorphous surface layer before the dopant implant.
For customers requiring ultra-shallow junctions with abrupt profiles, we recommend the full channeling suppression protocol: PAI + screen oxide + tilt + low-temperature anneal. This combination limits the as-implanted profile to within ~15nm of the surface while maintaining crystalline quality after RTA recrystallization.
Applications
CMOS Well & Channel Engineering
Retrograde well formation for latch-up suppression. Threshold voltage adjustment via channel implants. Halo/pocket implants for short-channel effect control. Multi-well isolation for mixed-signal and RF CMOS. Dopant profiles verified by SIMS and spreading resistance.
Power Device Doping
Deep junction formation for high-voltage diodes, IGBTs, and power MOSFETs. Field ring and JTE implants for edge termination. Backside emitter doping for IGBT and thyristor structures. High-energy P⁺ implants up to 3 MeV for deep n-type buried layers. Activation by furnace anneal for uniform carrier lifetime.
Image Sensor & Photodetector
Photodiode doping profile engineering for optimized quantum efficiency and dark current. Pinned photodiode implants for CMOS image sensors. Avalanche photodiode (APD) multiplication region doping — precise doping of the multiplication layer for controlled gain. Surface passivation implants to reduce dark current at Si-SiO₂ interface.
Radiation-Hard & Research
Custom doping profiles for radiation-hardened electronics, particle detectors, and research devices. Deep buried collectors for BJT and BiCMOS processes. Gettering layers via high-dose carbon or oxygen implants. Custom implant sequences for experimental devices — from fundamental semiconductor physics research to proof-of-concept prototypes.
Implant Damage & Recovery
Every ion impact displaces silicon atoms from their lattice sites, creating a cascade of point defects (vacancies and interstitials) along the ion track. At high doses, individual damage cascades overlap, forming a continuous amorphous layer from the surface to a depth determined by the ion energy and species. The critical dose for amorphization varies by ion mass: heavier ions like As⁺ and Sb⁺ amorphize Si at lower doses (~1×10¹⁴ cm⁻²) compared to lighter B⁺ (~1×10¹⁵ cm⁻²).
Annealing reverses implant damage through solid-phase epitaxial regrowth (SPER). The amorphous/crystalline interface advances toward the surface at rates of ~1–10 nm/s at 550–600°C. However, the end-of-range (EOR) damage — a band of dislocation loops just beyond the original amorphous/crystalline boundary — requires higher temperature annealing (900–1000°C) to dissolve. Our annealing protocols are optimized to achieve complete damage recovery while preserving the engineered doping profile.
Request Your Doping Recipe
Tell us your target species, dose, energy, and substrate specification. Our process engineers will recommend the optimal implant and anneal recipe and provide a detailed quote within 24 hours.