Silicon on Sapphire (SOS) Wafers for Rad-Hard Electronics
R-plane sapphire with epitaxial single-crystal (100) Si grown by <strong>CVD heteroepitaxy + SPE</strong>—built for <strong>low-loss RF</strong>, high-temperature operation, and radiation-hardened systems.
Product Overview
GINECHIP Silicon on Sapphire (SOS) wafers combine an R-plane sapphire insulator with a high-quality, single-crystal (100) Si layer grown via CVD heteroepitaxy + SPE for stable device fabrication.
Designed for harsh environments, SOS provides true dielectric isolation with <strong>no latch-up</strong> and <strong>high radiation tolerance</strong>, while maintaining low-defect and low-roughness requirements for RF and analog ICs.
Core advantages: <strong>dielectric isolation</strong>, <strong>no latch-up</strong>, and <strong>rad-hard performance</strong>.
Why Choose SOS
SOS provides <strong>all-dielectric isolation</strong> using sapphire as the insulator, enabling robust operation for power-limited and high-reliability electronics without latch-up risk.
With <strong>low defect density</strong>, controlled surface/interface quality, and <strong>rad-hard</strong> resilience above 100 krad(Si) with no latch-up, SOS is suitable for space, defense, and high-temperature platforms.
Silicon Film Quality
Single-crystal (100) Si on R-plane sapphire with <strong>XRD FWHM < 0.5°</strong> and <strong>RMS roughness < 0.5 nm</strong>, supporting stable film integrity for advanced device processes.
Wafer Reliability & Dimensional Control
<strong>TTV & bow control for lithography-ready wafers.</strong> SOS Si-on-sapphire wafers feature <strong>TTV < 5 μm</strong> and <strong>bow < 15 μm (150 mm)</strong>, supporting stable wafer handling, uniform patterning, and reliable process alignment. Available thickness: 330–650 μm with tight thickness uniformity for high-yield fabrication.
Thermal & Mechanical Performance
<strong>Designed for stable operation from cryogenic to high temperature.</strong> SOS sapphire/Si technology supports operation from <strong>-55°C to +300°C</strong>, with <strong>thermal conductivity of 40 W/m·K</strong>. This helps maintain electrical and process stability across temperature swings for demanding applications.
Deposition & Fabrication Process
CVD heteroepitaxial growth plus solid-phase epitaxy (SPE) forms a <strong>single-crystal (100) Si film</strong> on R-plane (1-102) sapphire, with thickness <strong>100nm-1000nm</strong>. The microtwin density is <strong><10^6/cm²</strong>, and the Si/sapphire interface is abrupt for reliable device performance.
SOS vs SOI Comparison
SOS uses a single-crystal sapphire insulator, while SOI relies on SiO₂ as the buried oxide. This table highlights the key trade-offs—especially for <strong>rad-hard performance</strong>, thermal stability, and RF behavior.
| Parameter | SOS | SOI |
|---|---|---|
| Buried Insulator | Sapphire (Al₂O₃, single crystal) | SiO₂ (amorphous) |
| Insulator εᵣ | 9.4–11.5 | 3.9 |
| Thermal Conductivity | 40 W/m·K (sapphire) | 1.4 W/m·K (SiO₂) |
| Radiation Hardness | > 100 krad(Si), no latchup | Up to 100 krad(Si), BOX trapping |
| Max Operating Temp | 300°C | 250°C |
| Substrate Loss (RF) | Extremely low (insulating sapphire) | Low, but HR-Si handle needed |
| Si Film Quality | Heteroepitaxial (defects at interface) | Single-crystal (smart-cut or BESOI) |
| Wafer Diameter | 2″–8″ | 100mm–300mm |
| Cost | $$$ | $$ |
Quality Assurance & Reliability
Quality assurance is verified via XRD FWHM <0.5° and defect density <10⁶/cm². Radiation hardness is accepted by lot using Co-60 to 100 krad(Si). Each wafer undergoes 100% inspection, and products ship vacuum-sealed in Class 100 packaging.
Specifications
| Parameter | Value / Specification |
|---|---|
| Base Substrate | R-plane (1-102) sapphire, 2″–8″ diameters, 330–650μm thick |
| Silicon Film Thickness | 100nm, 150nm, 200nm, 300nm, 500nm, 1000nm, ±10% tolerance |
| Deposition Method | CVD heteroepitaxial growth, solid-phase epitaxy |
| Silicon Crystal Quality | Single-crystal (100) Si on R-plane sapphire, FWHM < 0.5° XRD |
| Resistivity | Intrinsic: > 100 Ω·cm; N-type or P-type doped per specification |
| Mobility | Electron μₑ: 400–700 cm²/V·s; Hole μₕ: 150–250 cm²/V·s |
| Defect Density | Microtwin density reduced via SPE, < 10⁶/cm² |
| Surface Roughness | RMS < 0.5nm |
| TTV/Bow | TTV < 5μm, Bow < 15μm for 150mm |
| Buried Interface Quality | Si/Sapphire interface: abrupt, contamination < 5×10¹¹/cm² |
| Dielectric Isolation | Sapphire insulator: εᵣ = 9.4–11.5 |
| Thermal Conductivity | Sapphire: 40 W/m·K |
| Operating Temperature | -55°C to +300°C with appropriate metallization |
| Radiation Tolerance | > 100 krad(Si) total dose, no latchup |
| Packaging | Vacuum-sealed single-wafer cassette, Class 100 |
Applications
Radiation-Hardened CMOS
SOS is the premium substrate for radiation-hardened integrated circuits in space, defense, and nuclear applications. The insulating sapphire substrate completely eliminates latchup — the parasitic thyristor effect that destroys bulk CMOS ICs under heavy-ion or proton irradiation. SOS CMOS circuits withstand total ionizing dose (TID) exceeding 100 krad(Si) and single-event latchup (SEL) immunity to LET > 120 MeV·cm²/mg.
RF Switches & Front-Ends
The insulating sapphire substrate eliminates the conductive silicon handle wafer present in conventional SOI, dramatically reducing RF substrate losses. SOS RF switches achieve insertion loss < 0.3 dB and isolation > 30 dB at 2 GHz, with harmonic distortion (HD2/HD3) significantly lower than bulk CMOS or GaAs pHEMT alternatives. Essential for antenna tuning and band selection in multi-mode 4G/5G smartphones.
High-Temperature Electronics
SOS CMOS circuits operate reliably from -55°C to +300°C due to the full dielectric isolation eliminating junction leakage — the primary failure mechanism in bulk silicon at elevated temperatures. Applications include downhole oil and gas instrumentation, automotive engine compartment electronics, and jet engine sensor interfaces where conventional silicon fails above 200°C.
Integrated Photonics
SOS substrates combine a high-index silicon device layer (n = 3.47) on a moderate-index sapphire substrate (n = 1.77), providing sufficient index contrast for sub-micron optical waveguides while enabling evanescent coupling to the sapphire for mid-IR sensing. SOS photonic platforms operating at 1.55μm and in the mid-IR (3–5μm) are used for on-chip spectroscopy and chemical sensing.
X-Ray & Particle Detectors
SOS pixel detectors for high-energy physics experiments and synchrotron X-ray imaging benefit from the fully depleted, low-capacitance silicon film on an insulating substrate. The absence of a conductive bulk eliminates cross-talk between adjacent pixels, while radiation hardness ensures stable operation over years of high-flux exposure at facilities like CERN and synchrotron beamlines.
Aerospace & Satellite Systems
SOS technology has been deployed in over 200 satellite programs, including GPS Block III, Iridium NEXT, and Mars rover missions. The combination of radiation hardness, wide temperature range, and proven flight heritage (> 500 million device-hours in orbit) makes SOS the trusted substrate for mission-critical spacecraft avionics, star trackers, and communication payloads.
Metrology & Quality Control
Every wafer is inspected with metrology below. <strong>CoA is included with every shipment</strong>. Get <strong>100% parametric data</strong> for lot acceptance.
Source SOS Wafers
<strong>Custom thickness, doping, and diameters</strong> are available. Tell us your requirements and talk to our engineers.