Ultra-Thin / Taiko Wafers
Ultra-thin silicon wafers (as thin as 20μm) for 3D-IC stacking, power devices, and advanced packaging. Taiko wafer process leaves an unthinned outer ring for mechanical stability during backside processing. Backgrinding, CMP, stress relief, and dicing tape lamination available.
What is Ultra-Thin Wafer Thinning?
Ultra-thin wafer thinning is the mechanical, chemical, and plasma-based reduction of a standard-thickness silicon wafer (725–775μm) to final thicknesses as low as 20μm — thinner than a human hair. This capability is fundamental to modern semiconductor packaging technologies including 3D-IC stacking, through-silicon vias (TSVs), back-side illuminated image sensors, and high-voltage power devices where reduced substrate thickness directly translates into lower electrical resistance, improved thermal dissipation, and reduced package height.
Conventional backgrinding can reduce a wafer to approximately 50–100μm, but below this threshold the wafer becomes too fragile to handle — it warps under its own weight and shatters at the slightest mechanical perturbation. The Taiko process, pioneered by DISCO Corporation, solves this problem by leaving a full-thickness support ring (2–3mm wide) around the wafer edge while thinning only the central device area. This ring acts as a structural frame, enabling the wafer to survive subsequent lithography, etching, deposition, and TSV formation steps without carrier bonding.
At GINECHIP, we offer full-spectrum wafer thinning services from standard backgrind (100–200μm) through ultra-thin (20μm) and Taiko-process (30μm minimum thinned region) across 200mm and 300mm diameters. Our thinning workflow integrates rough grind, fine grind, CMP or dry polish, stress relief, and dicing-tape lamination — all performed in Class 1 cleanroom conditions with full metrology at every stage.
The Taiko Wafer Process
The Taiko process (named after the Japanese drum, whose shape it resembles) selectively thins the central region of the wafer while leaving a full-thickness ring at the periphery. This elegant solution provides mechanical rigidity without the cost and complexity of temporary carrier bonding and debonding.
The unthinned outer ring acts as a structural frame. It preserves wafer rigidity, prevents edge chipping, and allows the wafer to be handled by standard fab automation — no carrier required.
The recessed central area receives the full thinning sequence: rough grind → fine grind → stress relief → CMP. This is where TSVs, backside metal, and die stacking are performed.
Front-side processing is completed on full-thickness wafers before thinning. A protective tape is applied to the front side during backgrind. The device layer remains intact throughout the thinning sequence.
Wafer Thinning Process Stages
Ultra-thin wafer production follows a sequential multi-stage process. Each stage addresses a specific requirement: bulk material removal, damage minimization, surface quality, mechanical integrity, and safe handling. Skipping or under-performing any stage compromises die strength and yield.
Rough Grind
High-rate bulk silicon removal with coarse diamond wheel (#320–#600 grit)
Rough grinding removes the bulk of the silicon — typically 600–700μm — at high feed rates. A coarse-grit diamond wheel generates significant sub-surface damage (micro-cracks, dislocations) extending 3–5μm into the silicon. This damage layer must be removed in subsequent steps to restore die strength.
Fine Grind
Fine-grit wheel reduces sub-surface damage depth (#2000–#8000 grit)
A fine-grit diamond wheel removes the heavily damaged silicon layer left by rough grinding, reducing sub-surface damage depth by 70–80%. Spindle speed, feed rate, and coolant flow are tightly controlled to minimize new damage introduction. The wafer exits this stage with a matte finish and TTV typically < 3μm.
CMP / Dry Polish
Chemical-mechanical or dry polishing to mirror finish
CMP delivers the lowest surface roughness (< 0.5nm RMS) and eliminates residual grinding marks. Dry polishing is an alternative for wafers that cannot tolerate wet chemistry (e.g., completed MEMS structures). The choice between CMP and dry polish is application-dependent — CMP is preferred for TSV reveal and backside metallization; dry polish suits MEMS and some power devices.
Stress Relief
Wet etch or plasma removal of the mechanically damaged silicon layer
Stress relief is the single most critical step for die strength. Even fine grinding leaves a residual damage layer that acts as a crack-initiation site during dicing and packaging. A controlled isotropic etch removes this layer entirely, increasing die fracture strength from ~400 MPa (as-ground) to > 800 MPa — a 2× improvement essential for reliable thin-die packaging.
Dicing Tape Lamination
UV or thermal-release tape mounting for safe handling through dicing
After thinning and stress relief, the wafer is laminated with dicing tape on the backside and mounted to a rigid frame. UV-release tapes lose adhesion upon UV exposure (typically 365nm, 200–500 mJ/cm²), enabling clean die pick-up after singulation. Thermal-release tapes debond at elevated temperature (120–180°C). Tape selection depends on die size, downstream assembly process, and thermal budget.
Technical Specifications
| Parameter | Available Range / Values |
|---|---|
| Wafer Diameter | 200mm (8″), 300mm (12″) |
| Starting Thickness | 725μm (200mm), 775μm (300mm) — standard prime |
| Minimum Final Thickness | 20μm (conventional backgrind), 30μm (Taiko ring) |
| Taiko Ring Width | 2–3mm from wafer edge, full original thickness retained in ring |
| TTV After Thinning | < 2μm (within thinned area), < 3μm overall (conventional) |
| Surface Roughness After CMP | < 0.5nm RMS (AFM, 1×1μm scan) — mirror finish |
| Sub-Surface Damage (SSD) | < 1μm after stress relief; < 0.2μm after CMP finish |
| Die Strength (3-Point Bend) | > 800 MPa (stress-relieved); > 400 MPa (rough grind only) |
| Dicing Tape Type | UV-release (PO, PET base), thermal-release, non-UV (standard) |
| Backside Metal | Ti/Ni/Ag, Ti/Ni/Au, AuSn solder — sputtered or evaporated, on request |
| Wafer Type | Standard, HR-Si, SOI device layer thinning, SiGe, GaAs-on-Si |
Applications & Market Segments
3D-IC & Advanced Packaging
Ultra-thin wafers (30–100μm) enable through-silicon via (TSV) formation, die stacking with microbumps, and chip-on-wafer hybrid bonding for HBM memory and chiplet architectures. Taiko ring provides mechanical integrity during TSV processing.
Power Devices (IGBT/MOSFET)
Thinned IGBTs and power MOSFETs (60–120μm) reduce on-state resistance (Ron) and improve thermal impedance to the heatsink. Backside grinding enables field-stop and punch-through vertical device structures.
Back-Side Illuminated (BSI) Sensors
CMOS image sensors requiring back-side illumination must be thinned to 5–20μm so that photons reach the photodiode from the back surface. Taiko wafer processing is the industry-standard approach for BSI CIS production.
Stacked Memory (HBM / NAND)
High-bandwidth memory and 3D NAND flash stacks use ultra-thin die (30–50μm) to maximize the number of die per package within a fixed z-height. Thinning uniformity is critical for consistent bond-line thickness.
Discrete & RF Power
RF LDMOS, GaN-on-Si HEMT, and discrete power diodes on thinned substrates (50–100μm) improve thermal dissipation and reduce source inductance for better RF gain and efficiency.
Flexible & Medical Electronics
Silicon thinned below 30μm becomes mechanically flexible. Used in implantable medical sensors, neural probes, and conformable electronics where substrate compliance is required.
Metrology & Quality Assurance
Thin-wafer metrology is exceptionally demanding because standard contact and capacitance gauges can fracture wafers below 100μm. Our protocol combines non-contact optical techniques with destructive sample testing to provide a complete quality picture.
Need Ultra-Thin or Taiko Wafers?
Specify your wafer diameter, target thickness, Taiko ring requirement, stress-relief preference, and dicing tape type — our thinning specialists will provide a process qualification plan and quotation within 24 hours.