Advanced Packaging — 2.5D, 3D-IC, FOWLP, RDL, TSV Substrates | GINECHIP

2.5D · 3D-IC · FOWLPPackaging Architectures

L/S 0.4/0.4μmMin. RDL Pitch

TSV · TGV · μ-BumpKey Packaging Technologies

TB/s/mmInterconnect Bandwidth

Overview

A comprehensive overview of our capabilities and services.

We deliver industry-leading quality and precision.

Packaging Technologies

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Interposer: 300mm Si, 100μm thickTSV: 10μm dia, 100μm deep, AR 10:1RDL: Cu damascene, 2–5 layersL/S: 0.4/0.4μm minimumμ-bump pitch: 40–55μmC4 bump pitch: 130–150μm

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Stack height: 2–12 dieμ-bump pitch: 10–40μmHybrid bond pitch: < 1μm (R&D)TSV: 5μm dia, 50μm deepWafer thinning: < 50μmTemp: TCB or mass reflow

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Die shift: < 2μmRDL: Cu, 2–5 layers, L/S 2/2μmMold compound: EMCBall pitch: 300–500μmPackage thickness: < 0.5mmWafer: 200mm or 300mm recon

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RDL L/S: 1/1μm (Cu damascene)Dielectric: polyimide or SiO₂Multi-die integrationPassive integration (IPD)Shielding: Cu backside metalWafer: 300mm

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Laminate: BT, ABF, or corelessDie thickness: 50–100μmMicrovia: 30–60μm diaL/S: 8/8μm (mSAP)Embedded passives possiblePanel-level processing option

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Glass: borosilicate, fused silicaTGV: 20–50μm dia, AR 6:1Metallization: Cu-filled TGVCTE: 3–8 ppm/K (tunable)Panel: up to 510×515mmLoss tangent: < 0.005 @ 10GHz

Available Process Services

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Key Application Areas

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RDL Design Rules

Parameter	Standard RDL (≤ 10μm L/S)	Fine-Line RDL (≤ 5μm L/S)	Ultra-Fine RDL (≤ 2μm L/S)
Minimum L/S	5/5μm	2/2μm	0.4/0.4μm
Cu Thickness	5–8μm	3–5μm	1–3μm
Via Diameter	20–30μm	10–15μm	5–10μm
Dielectric	Polyimide (PID)	Polyimide or BCB	SiO₂ (CVD)
Dielectric Constant (k)	3.0–3.5	2.6–3.0	3.9 (SiO₂)
Number of Layers	1–3	2–5	2–8
Cu Deposition Method	Semi-additive (SAP)	SAP or Damascene	Cu Damascene
Planarization	None or CMP	CMP	CMP (per layer)

Substrate Selection

Substrate Selection Paragraph

Quality & Metrology

Quality Description

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ISO 9001:2015 JEDEC Standards TSV · RDL · Bump 3D Integration