Process Selection Guide
processSelectionGuide.desc
Overview
Process Guide Intro
Representative Process Flows
MEMS Inertial Sensor Flow
Starting substrate → Thermal SiO₂ isolation → Si₃N₄ protection → DRIE structural etch → HF vapor release → Wafer bonding hermetic cap
CMOS SOI Device Flow
SOI wafer (pre-bonded or SIMOX) → STI trench etch and fill → Gate stack (thermal SiO₂ + poly-Si or high-k/metal) → Spacer (LPCVD Si₃N₄ + RIE) → Silicidation → PECVD ILD/damascene metallization
GaN HEMT Power Device Flow
GaN-on-Si epi-wafer → Mesa isolation (DRIE or RIE) → Gate recess AlGaN etch → Gate metallization (Ni/Au or TiN) → Passivation (PECVD SiNx) → Ohmic contact (Ti/Al/Ni/Au) → Field plate and final passivation
TSV & 3D Interposer Flow
Device wafer → TSV DRIE (10:1 AR, Bosch) → Sidewall liner (thermal SiO₂ or ALD Al₂O₃) → Barrier/seed PVD (TiW/Cu) → TSV Cu electroplating fill → CMP planarize → Backside thinning (grind + CMP) → TSV reveal → RDL build
Silicon Photonics PIC Flow
SOI wafer (220nm Si / 2μm BOX) → Waveguide pattern (DUV or e-beam litho) → Si etch (cryo or Bosch DRIE) → SiO₂ upper cladding PECVD → CMP planarize → Grating coupler etch → Ge epitaxy for photodetectors → Metal contacts → Dicing and fiber attach
SAW / BAW Filter Flow
Piezoelectric substrate (LiNbO₃ or AlN/Si) → IDT metallization (Al, 100–200nm) → Lift-off patterning or RIE etch → Wafer-level cap bonding (Si or glass cap) → Hermetic seal (eutectic Au–Sn) → Dicing and package
Power SiC MOSFET Flow
4H-SiC substrate + n-type epi → P-well implant (Al, high-T activation 1700°C) → Gate oxide (thermal + NO anneal) → Poly-Si gate → ILD (PECVD SiO₂/SiNx) → Ohmic contacts (Ni, RTA) → Source metal (Al) → Final passivation → Backside drain (Ni/Ag)
Microbolometer / IR Sensor Flow
CMOS ROIC wafer → Sacrificial polyimide → Sensing layer (VOx or a-Si) → Electrode via etch → Metal reflector → Sacrificial layer release (O₂ plasma ashing) → Wafer-level vacuum packaging (Si cap with getter, eutectic bond)
Fan-Out WLP Flow
Known-good die → Face-down placement on carrier → EMC molding → Carrier debond → RDL build (PECVD ILD + Cu plating, 1–4 layers) → UBM → Solder bump or Cu pillar → Backside protect → Test and singulation
How To Use Guide
Process Guide Usage