Prime Silicon Wafers
Device-grade prime silicon wafers — the highest quality classification for semiconductor manufacturing. CZ and FZ growth methods, sub-nanometer surface roughness, tight resistivity and thickness tolerances. 100mm–300mm diameters for CMOS, MEMS, power devices, and advanced packaging lines.
Device-Grade Prime Silicon Wafers
Prime-grade silicon wafers represent the highest quality classification of single-crystal silicon substrates in the SEMI M1–M13 standard hierarchy. Each prime wafer is produced from ultrapure polysilicon feedstock (9N–11N purity) and is subjected to rigorous crystal growth, wafering, chemical-mechanical polishing, and cleaning processes to meet the exacting cleanliness, flatness, and crystallographic perfection required by semiconductor device fabrication.
The global prime silicon wafer market exceeded USD 12 billion in annual shipments, driven by the relentless demand for logic, memory, power, and analog ICs across data centers, smartphones, automotive electrification, and IoT edge devices. At advanced CMOS nodes (sub-5nm), a single prime wafer must maintain particle counts below 10 at 0.2μm and surface roughness below 0.2nm RMS — specifications that demand extraordinary control over every step of the manufacturing supply chain.
At GINECHIP, we supply device-grade prime wafers grown via CZ, MCZ, and FZ methods across all standard diameters from 100mm to 300mm. Every lot includes a full Certificate of Analysis (CoA) documenting resistivity, thickness, TTV, bow, warp, surface roughness, particle counts, and oxygen/carbon content per SEMI and ASTM standards. COP-free argon-annealed options, backside poly-silicon gettering, and custom off-cut orientations are available on request.
Crystal Growth Methods
Three distinct single-crystal growth technologies produce prime silicon wafers, each optimized for different device performance requirements. Selecting the right growth method is the single most impactful decision in substrate specification.
CZ (Czochralski)
Melt-growth from a crucible — industry standard
The workhorse of the semiconductor industry. A single-crystal seed is dipped into molten silicon and slowly pulled upward while rotating, producing ingots up to 300mm diameter and 2m+ length. High throughput, moderate oxygen content (12–18 ppma), and excellent cost efficiency for CMOS, logic, memory, and MEMS applications.
MCZ (Magnetic CZ)
Magnetic-field-stabilized Czochralski growth
CZ growth with a strong horizontal magnetic field applied to the melt. The Lorentz force suppresses thermal convection, reducing oxygen incorporation by 30–50% and dramatically improving resistivity radial uniformity. Preferred for power semiconductors (IGBTs, MOSFETs) where precise oxygen control governs lifetime-killer behavior and for high-resistivity substrates used in RFICs.
FZ (Float Zone)
Crucible-free zone-refining — ultimate purity
A molten zone passes along a polycrystalline rod under RF induction in vacuum or inert gas, refining the silicon to extreme purity levels. No crucible contact means carbon and oxygen are below IR detection limits (＜ 0.1 ppma). Achieves the highest resistivity (up to 10,000+ Ω·cm) and longest minority carrier lifetimes (＞ 1,000 μs). Essential for high-voltage discrete power devices, photodiodes, RF substrates, and terahertz optics.
Grade Comparison: CZ vs MCZ vs FZ
The choice between CZ, MCZ, and FZ substrates depends on the target device's requirements for oxygen content, resistivity range, defect density, and cost sensitivity. The table below summarizes key differentiating factors.
CZ (Czochralski)
Standard melt-growth in a quartz crucible. Moderate oxygen content (12–18 ppma) provides beneficial internal gettering of metallic contaminants. Economical at all diameters up to 300mm.
MCZ (Magnetic CZ)
Magnetic field suppresses melt convection, reducing oxygen by 30–50% and improving radial resistivity uniformity. Optimal for power semiconductors requiring controlled oxygen levels.
FZ (Float Zone)
Crucible-free growth with impurity levels below IR detection. Highest resistivity (＞ 10 kΩ·cm), longest carrier lifetime (＞ 1,000 μs), and lowest oxygen (＜ 0.1 ppma).
COP-Free & Annealed Prime Wafers
Crystal-Originated Particles (COPs) are nanometer-scale vacancy-aggregate voids formed during CZ crystal growth — ranging from 30nm to 200nm in diameter. When these voids intersect the polished wafer surface, they appear as light-scattering events indistinguishable from true surface particles during laser inspection, causing false defect counts that degrade gate oxide integrity (GOI) yield in advanced CMOS processes.
To address this, GINECHIP offers argon-annealed prime wafers per SEMI M78. A high-temperature anneal (≥ 1,200°C) in argon or hydrogen ambient dissolves COPs in the near-surface region (typically 3–10μm depth), producing a COP-free denuded zone while preserving bulk oxygen precipitates for internal gettering deeper in the wafer. This treatment is essential for device layers requiring gate oxide thicknesses below 3nm at sub-28nm technology nodes.
Technical Specifications
| Parameter | Available Range / Values |
|---|---|
| Growth Method | CZ (Czochralski), FZ (Float Zone), MCZ (Magnetic CZ) |
| Diameter | 100mm (4″), 125mm (5″), 150mm (6″), 200mm (8″), 300mm (12″) |
| Dopant Type | N-type (Phosphorus, Arsenic, Antimony) / P-type (Boron) |
| Resistivity Range | 0.001 – 10,000 Ω·cm (application-dependent) |
| Crystal Orientation | 〈100〉, 〈111〉, 〈110〉 (off-cut ±0.5° to ±4° on request) |
| Oxygen Content | 12 – 18 ppma (ASTM F121-80), tailored for internal gettering |
| Carbon Content | ≤ 0.1 ppma (ASTM F1319), ultra-low for power devices |
| Thickness Range | 200μm – 1,000μm+ (SEMI M1–M13 standard thicknesses) |
| Thickness Tolerance | ±5μm (200mm), ±10μm (300mm), ±15μm (smaller diameters) |
| TTV (Total Thickness Variation) | ≤ 2μm (200mm), ≤ 3μm (300mm, GBIR per SEMI M1) |
| Bow / Warp | ≤ 20μm Bow, ≤ 25μm Warp (200mm); ≤ 30μm Bow, ≤ 40μm Warp (300mm) |
| Surface Roughness (AFM RMS) | ＜ 0.2nm (1×1μm scan) — Epi-Ready finish |
| Polish Type | SSP (Single-Side Polished) / DSP (Double-Side Polished) |
| Edge Profile | SEMI standard: Round, T-Edge, or E-Edge per diameter |
| Particles @ 0.2μm | ≤ 10 particles (SEMI M53, laser surface scan) |
| COP-Free Option | Argon or Hydrogen annealed — near-zero COPs in near-surface region |
| Backside Treatment | Etched, polished, or poly-silicon back-seal for gettering |
| Laser Mark | SEMI M12/M13 compliant: soft-mark on front or back side |
| Flat / Notch | Per SEMI M1: primary/secondary flats or single notch (200mm/300mm) |
| Warp Control | Edge-Grip or conventional polishing for ultra-flat requirements |
| Packaging | Class 100 cleanroom vacuum-sealed cassette or single-wafer shippers |
| Compliance | SEMI M1–M13, SEMI M53, RoHS, REACH |
Applications & Market Segments
CMOS Logic & Memory
The backbone of the USD 550B semiconductor industry. Prime CZ wafers serve as starting substrates for microprocessors, DRAM, NAND flash, and SoCs at nodes from 180nm to sub-3nm. Tight particle and surface specifications ensure photolithography yield at advanced nodes.
MEMS & Sensors
Micro-electromechanical systems rely on precisely specified CZ wafers for inertial sensors (accelerometers, gyroscopes), pressure sensors, microphones, and micro-mirrors. DSP wafers with controlled TTV are critical for DRIE etch-through processes and wafer-bonding compatibility.
Power Devices
IGBTs, super-junction MOSFETs, SiC-on-Si epitaxy, and high-voltage diodes demand FZ wafers with resistivity exceeding 1,000 Ω·cm and ultra-low oxygen. MCZ substrates provide the controlled oxygen environment required for optimal lifetime engineering in high-speed power switches.
CMOS Image Sensors (CIS)
Prime wafers with epitaxial silicon layers on heavily-doped substrates provide the gettering capacity and low dark-current characteristics essential for smartphone, automotive, and industrial image sensors. Epi-ready surface quality with sub-0.2nm RMS roughness ensures defect-free epitaxial growth.
Analog / Mixed-Signal
Precision analog ICs — operational amplifiers, ADCs, DACs, voltage references — require wafers with tight resistivity tolerance and minimal dopant striations. FZ substrates with exceptional radial uniformity are preferred for high-performance analog where matching is critical.
Silicon Photonics & Optics
FZ high-resistivity silicon provides the low-loss, low-dispersion optical medium for silicon photonic integrated circuits operating from 1.1μm to 6μm. CZ wafers are used for wafer-level optics, diffractive elements, and structured surfaces in consumer and industrial photonics.
Metrology & Quality Assurance
Every prime wafer lot is characterized through a multi-technique metrology protocol at ISO 9001:2015 certified facilities. A comprehensive Certificate of Analysis (CoA) documenting all measured parameters is provided with each shipment.
Need Prime Wafers for Your Fab?
Specify your diameter, growth method (CZ/MCZ/FZ), dopant type, resistivity range, orientation, and quantity — our substrate specialists will provide a detailed quotation with metrology data and lead time within 24 hours.