SEMI Standards Reference — Wafer & Substrate Specifications | GINECHIP

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Stat Value 2Resolution

Stat Value 3Capacity

Stat Value 4Certification

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H 2Main Standards

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直徑：50.8mm–450mm（2吋–18吋）晶向：〈100〉, 〈110〉, 〈111〉替代摻雜：p-type (Boron)、n-type (Phos, As, Sb)Notch：SEMI M1 附錄對 notch 尺寸規範標記：SEMI 字母數字與條碼規範修訂：持續更新，最新版 2023 年 4 月

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外延厚度：0.5μm–150μm厚度均勻性：±2%–±5%電阻率：0.001–1000 Ω·cm缺陷：滑移線、堆垛層錯、Haze襯底：As-doped, Sb-doped, 或 intrinsic應用：CMOS, BiCMOS, 功率元件

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GaAs：2吋–6吋（50.8mm–150mm）InP：2吋–4吋（50.8mm–100mm）EPD：< 5×10³ cm⁻² (LED) 至 < 5×10⁴ cm⁻² (IC)晶向：(100), (111)A, (111)B摻雜：Si-doped n-type, Zn-doped p-type應用：RF, 光電, LED, 太陽能電池

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測量：激光表面掃描（SP1, SP2, SP3）粒徑級別：≥0.09μm, 0.12μm, 0.16μm...邊緣排除：3mm (150mm), 5mm (200mm)COPs：晶體原生顆粒處理先進節點：≥19nm 顆粒 < 10/晶圓報告：每片晶圓顆粒數 + 累積分佈

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方法：VPD-ICP-MS, TXRF, SIMS元素：Fe, Cu, Ni, Cr, Na, Al, Zn, Ca...先進節點：< 1×10¹⁰ atoms/cm² 總金屬關鍵元素：Cu < 5×10⁹, Fe < 1×10¹⁰表面製備：SC1/SC2 清洗後測量分級：Grade 1 (最嚴格) 至 Grade 4

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頂層 Si：5nm (FD-SOI) 至 100μm (電源)BOX：10nm–2μm SiO₂均勻性：±5Å (FD-SOI), ±0.5μm (厚膜)製備：Smart Cut™, BESOI, SIMOX缺陷：HF 缺陷, 空洞 (voids)應用：FD-SOI, RF-SOI, 光子 SOI, 功率 SOI

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多型：4H-SiC, 6H-SiC直徑：100mm, 150mm, 200mm (新興)MPD：< 0.1 cm⁻² (Prime), < 0.5 cm⁻² (標準)BPD：< 500 cm⁻² 磊晶後表面：CMP Ra < 0.2nm, epi-ready應用：電動車逆變器、5G GaN RF、電網

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基板：GaN-on-Si, GaN-on-SiC, GaN-on-藍寶石直徑：100mm, 150mm, 200mmXRD FWHM：(002) < 300 arcsec, (102) < 400翹曲：bow < 30μm (150mm)GaN 厚度：1μm–6μm應用：功率 HEMT, RF, microLED

H 2Test Methods

Test Methods Intro

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H 2How To Use

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H 2Param Ref

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H 2Evolution

Redistribution layer technology has evolved from simple peripheral pad rearrangement to complex multi-layer interconnect systems. Modern RDL integrates fine-pitch routing, integrated passive devices, and advanced dielectric materials to meet the demands of 2.5D and 3D packaging.

The transition from wafer-level packaging to panel-level processing promises further cost reduction and throughput improvement. Our RDL platform is designed for scalability from R&D volumes to high-volume manufacturing on both wafer and panel formats.

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