SEMI Standards Reference
Quick reference for key SEMI standards applicable to semiconductor wafers and substrates — M1, M53, M59, and more.
Overview
SEMI standards define the common specifications, test methods, and terminology that keep the global wafer supply chain interoperable — from wafer dimensions (M1) to particle counting (M53) to flatness metrology (M59). This reference summarizes the standards most relevant to sourcing and qualifying substrate materials.
Standards referenced here are current SEMI International Standards revisions used in our internal process documentation and customer specification sheets. Contact our engineering team for guidance on mapping your internal specifications to the applicable SEMI standard.
Key SEMI Standards
SEMI M1 — Polished Monocrystalline Silicon Wafers
Defines diameter, crystal orientation, doping type, notch geometry, and wafer marking requirements for polished monocrystalline silicon wafers from 50.8mm to 450mm, forming the baseline specification referenced by most other wafer standards.
Epitaxial Silicon Wafer Specifications
Covers epitaxial layer thickness, thickness uniformity, resistivity, and defect criteria (slip lines, stacking faults, haze) for silicon epi wafers used in CMOS, BiCMOS, and power device fabrication.
Compound Semiconductor Wafer Specifications (GaAs / InP)
Specifies diameter, etch pit density, crystal orientation, and doping requirements for GaAs and InP compound semiconductor wafers used in RF, optoelectronic, LED, and photovoltaic applications.
SEMI M53 — Particle Count & Surface Scanning
Establishes laser surface-scanning methodology and particle size binning for detecting crystal-originated particles (COPs) and surface defects, with edge-exclusion zones scaled to wafer diameter.
Surface Metallic Contamination Specifications
Sets acceptance limits for trace metal contamination (Fe, Cu, Ni, Cr, Na, and others) measured by VPD-ICP-MS, TXRF, or SIMS after SC1/SC2 cleaning, graded from Grade 1 (tightest) to Grade 4.
SOI Wafer Specifications
Defines top-silicon and buried-oxide (BOX) thickness, uniformity, and defect requirements for silicon-on-insulator wafers produced by Smart Cut™, BESOI, or SIMOX, spanning FD-SOI, RF-SOI, and power SOI variants.
SiC Wafer Specifications (4H / 6H)
Specifies polytype, diameter, micropipe density (MPD), and basal-plane dislocation (BPD) limits for 4H-SiC and 6H-SiC wafers used in EV inverters, 5G GaN RF, and grid power applications.
GaN-on-Substrate Epitaxial Wafer Specifications
Covers substrate options (Si, SiC, sapphire), XRD rocking-curve linewidth, bow, and GaN epitaxial thickness for GaN-on-substrate wafers used in power HEMTs, RF devices, and microLEDs.
Test Methods
Each standard specifies validated test methods and equipment for consistent, repeatable measurement across suppliers and fabs.
Measures bulk resistivity by passing current through two outer probes and reading voltage across two inner probes in a linear array, correlating directly to dopant concentration.
Fourier-transform infrared spectroscopy quantifies interstitial oxygen and substitutional carbon concentrations in silicon, critical for controlling oxygen precipitation during device thermal cycles.
Non-contact capacitive or optical scanning determines TTV, bow, warp, and site-based flatness (SFQR) across the full wafer surface without mechanical clamping.
Automated laser light-scattering systems detect and bin surface particles and crystal-originated particles (COPs) down to sub-90nm size thresholds for advanced-node qualification.
How to Use These Standards
Incoming Quality Inspection
Use the parameter thresholds above to define acceptance criteria and reject limits when auditing incoming wafer lots against supplier certificates of conformance.
Supplier & Fab Qualification
Reference the same SEMI test methods your suppliers use so measurement results are directly comparable when qualifying a new fab or approving a second source.
Custom Specification Drafting
Start from the relevant SEMI baseline and tighten only the parameters that matter for your process node, avoiding unnecessarily restrictive specs that inflate cost.
Cross-Fab Process Transfer
Align wafer geometry and contamination specs to SEMI terminology so process recipes transfer predictably between internal fabs or outsourced foundries.
Parameter Reference
The parameters below appear across multiple SEMI standards and form the common vocabulary for wafer geometry and quality specifications.
The difference between the maximum and minimum thickness measured across a wafer, per SEMI MF1530.
Deviation of the wafer's median surface from a reference plane at its center point, measured unclamped, per SEMI MF1390.
The difference between the maximum and minimum distances of the median surface from a reference plane, per SEMI MF1390.
Site Front-surface-referenced least-squares Range — a site-based flatness metric used for lithography focus budgeting, defined in SEMI M1.
The annular region near the wafer edge excluded from flatness and particle specifications, per SEMI M59.
The crystallographic reference feature used to indicate wafer orientation and conductivity type, defined in SEMI M1.
Trace metal concentration on the wafer surface, measured per SEMI MF1724 using TXRF or VPD-ICP-MS.
The number of light-point defects on the wafer surface at a specified size threshold, measured per SEMI M50.
Standards Evolution
SEMI wafer standards have evolved alongside the industry's shift to larger diameters and tighter lithography tolerances. Early 100mm and 150mm specifications relied on primary flats for orientation, while 200mm and 300mm standards moved to notch-based referencing to support high-throughput automated handling.
As device geometries shrink and depth-of-focus budgets tighten, flatness metrics have shifted from whole-wafer measures like TIR toward site-based metrics such as SFQR, which better capture the local flatness that matters within a single lithography exposure field.
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