Wafer Bonding
Permanent and temporary wafer bonding technologies — anodic, fusion, eutectic, thermocompression, and adhesive. From MEMS hermetic sealing to 3D-IC die stacking.
Overview
Wafer bonding joins two substrates — typically wafers of the same or different materials — to form a permanent or temporary mechanical, electrical, and/or hermetic connection. It is a critical process step across MEMS packaging, SOI substrate manufacturing, 3D integrated circuit stacking, and advanced photonic device fabrication.
GINECHIP offers a complete portfolio of wafer bonding technologies under one quality system: anodic bonding for silicon-glass hermetic sealing, silicon fusion bonding for SOI fabrication and permanent wafer stacks, eutectic bonding for metal-sealed hermetic MEMS packages, thermocompression bonding for 3D-IC Cu-Cu interconnects, adhesive bonding for heterogeneous material integration at low temperature, and temporary bonding/debonding for thin-wafer handling during backside processing. Alignment accuracy below 2μm with infrared and cross-wafer alignment options.
Bonding Technologies
Anodic Bonding (Si–Glass)
Electrostatic bonding of silicon to sodium-containing glass (borosilicate, Pyrex®) at elevated temperature (300–500°C) under high voltage (400–1000V). Mobile Na⁺ ions in the glass drift toward the cathode, creating a strong electrostatic attraction and irreversible Si–O chemical bond at the interface. The industry-standard process for MEMS hermetic cavity sealing, pressure sensor encapsulation, and silicon-glass microfluidic devices.
Silicon Fusion Bonding (Si–Si / Si–SiO₂)
Direct wafer bonding of silicon or oxidized silicon surfaces without intermediate layers. Requires ultra-clean, smooth surfaces (Ra < 0.5nm) with hydrophilic surface activation (RCA-1 clean or plasma treatment). Room-temperature pre-bond followed by high-temperature anneal (800–1100°C) to achieve bulk-fracture-strength bonds. Essential for SOI substrate fabrication, 3D MEMS stacking, and wafer-level vacuum packaging.
Eutectic Bonding (Au–Si, Au–Sn, Al–Ge)
Metal-based bonding where a eutectic alloy forms at the interface at a specific temperature lower than the melting points of the individual metals. Au–Si eutectic (363°C, 3.7 wt% Si) and Au–Sn (280°C, 80 wt% Au) are widely used for MEMS hermetic packaging and LED die attach. Provides both mechanical bond and electrical interconnection in a single process step.
Thermocompression Bonding (Cu–Cu, Au–Au)
Solid-state diffusion bonding of metal surfaces under simultaneous heat and pressure without melting. Cu–Cu bonding at 300–400°C with 30–60 MPa pressure achieves low-resistance, high-reliability interconnects for 3D-IC stacking. Au–Au bonding at lower temperature (200–300°C) for hermetic MEMS packaging with fluxless, clean process.
Adhesive Bonding (Polymer)
Wafer bonding using organic adhesive interlayers — BCB (benzocyclobutene), SU-8, polyimide, or UV-curable epoxy. Operates at low temperatures (RT–250°C) with moderate bond strength. Tolerates surface roughness and topography (up to several microns) that would prevent direct or anodic bonding. Ideal for heterogeneous integration and temporary bonding applications.
Temporary Bonding & Debonding
Reversible bonding for thin-wafer handling during backside processing. Thermoplastic or laser-release adhesives temporarily bond the device wafer to a rigid carrier (Si or glass). After backside processing (thinning, TSV reveal, backside metallization), the carrier is removed by thermal slide, mechanical peel, or laser ablation.
Typical Applications
Si–SiO₂ fusion bonding + grind/polish to create silicon-on-insulator wafers with precise device layer and buried oxide thicknesses for CMOS, MEMS, and silicon photonics applications.
Wafer-level anodic (Si–glass), eutectic (Au–Si/Au–Sn), or fusion bonding of cap wafers to device wafers for permanent hermetic cavity sealing of inertial sensors, RF-MEMS, and resonators.
Cu–Cu thermocompression bonding and hybrid bonding for die-to-wafer and wafer-to-wafer stacking in 3D integrated circuits and high-bandwidth memory (HBM) with > 1 TB/s/mm bandwidth.
Anodic or adhesive bonding of patterned silicon to glass for microfluidic channels, lab-on-chip devices, and bio-MEMS platforms requiring optical access through transparent glass covers.
Temporary bonding of device wafers to carrier wafers for safe handling during backside thinning, TSV reveal, backside implant/anneal, and backside metallization. Debonding after processing.
Direct bonding of ion-sliced LiNbO₃ thin films to SiO₂-on-Si or SiO₂-on-LiNbO₃ handle wafers for electro-optic modulator fabrication — emerging platform for next-gen optical transceivers.
Bond Quality Inspection
Every bonded wafer pair is inspected using: C-mode scanning acoustic microscopy (CSAM) for void and delamination detection with μm-level resolution, infrared transmission imaging for Si-Si and Si-glass bond interface visualization, razor blade insertion test (Maszara method) for bond strength measurement, and helium leak testing for hermeticity verification per MIL-STD-883. Bond strength, void percentage, and hermeticity data are included in the process report delivered with each lot.
Need Wafer Bonding for Your Process?
Specify the materials to be bonded, required bond type, cavity requirements (if any), and alignment precision — our engineers will provide a technical recommendation and quotation within 24 hours.