Through-Silicon Via (TSV)

Stat Value 1Technology

Stat Value 2Resolution

Stat Value 3Capacity

Stat Value 4Certification

H 2Overview

A comprehensive overview of our capabilities and services.

We deliver industry-leading quality and precision.

H 2Modules

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Vias: 5–100μm diameterDepth: 20–300μmAspect ratio: up to 15:1Sidewall angle: 89° ± 0.5°Scallop control: < 50nmCryogenic smooth etch option

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Thermal SiO₂: 100nm–2μmPECVD SiO₂/Si₃N₄: 50–500nmConformality: > 90% (thermal), > 70% (PECVD)Breakdown: > 8 MV/cm (thermal)Process temp: 900–1100°C (thermal), 250–400°C (PECVD)Capacitance: 50–200 pF/via (design dependent)

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Barrier: Ta (PVD), TaN (PVD/ALD)Seed: Cu (PVD), 100–500nmBarrier thickness: 5–50nmStep coverage: > 25% (bottom, PVD)ALD barrier: > 95% conformalityAdhesion: no delamination after anneal

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Cu thickness: 3–25μm overfieldFill type: bottom-up superfillingChemistry: CuSO₄/H₂SO₄ + additivesPlating rate: 0.3–1.0 μm/minPost-plate anneal: 200–400°C, N₂X-ray inspection for void detection

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Cu removal rate: 300–600 nm/minCu dishing: < 50nmDielectric erosion: < 30nmPost-CMP Ra: < 1nm (AFM)Clean: particles < 20 adds @ 0.2μmNi/Au finish: 3–5μm Ni, 0.05–0.2μm Au

H 2Flow Opts

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TSV after FEOL, before BEOLVia diameter: 5–20μmThermal budget: compatible with BEOLAdvantage: dense TSV arraysChallenge: Cu protrusion during BEOL thermal cycles

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TSV after BEOL, from backsideVia diameter: 20–100μmThermal budget: < 400°C maxAdvantage: no FEOL/BEOL disruptionChallenge: alignment to buried pads

H 2Process Flow

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H 2Quality

Col Param	Col Target	Col Method
throughSiliconViaTsv.qm1Param	< 50 mΩ (typical, 10×100μm via)	4-point Kelvin probe on test structures
throughSiliconViaTsv.qm2Param	> 99.9% (1,000-via chain)	4-point resistance continuity
throughSiliconViaTsv.qm3Param	> 50V (for 200nm thermal SiO₂)	Ramped voltage I-V sweep
throughSiliconViaTsv.qm4Param	< 1 nA at 5V (silicon-to-TSV)	I-V measurement, Si grounded, TSV biased
throughSiliconViaTsv.qm5Param	< 100nm @ 400°C anneal	AFM / profilometry
throughSiliconViaTsv.qm6Param	Zero voids > 1μm in fill	X-ray microscopy / acoustic microscopy
throughSiliconViaTsv.qm7Param	< 50nm (Bosch process)	SEM cross-section
throughSiliconViaTsv.qm8Param	50–200 pF (dependent on geometry)	C-V measurement at 1 MHz

Quality Note

H 2Via Fill

Polyimide via filling creates planarized interlayer dielectrics with excellent gap-fill capability. The spin-on application fills high-aspect-ratio vias without voids, and the thermal curing process ensures homogeneous material properties throughout the filled structures.

Our via-fill polyimide process achieves aspect ratios up to 3:1 with void-free filling, as verified by cross-sectional SEM. The planarization capability reduces topography for subsequent lithography steps, improving CD uniformity across the wafer.

Photosensitive polyimide formulations enable direct patterning of via openings without separate photoresist processing. This reduces process steps by 30% while achieving via resolution down to 5μm.

H 2App Domains

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H 2Barrier

Polyimide serves as an excellent stress buffer layer between silicon substrates and subsequent metal or dielectric layers. Its low elastic modulus (~3 GPa) and high elongation (>30%) absorb thermal-mechanical stress during packaging and thermal cycling.

As a passivation layer, polyimide provides excellent chemical resistance, moisture barrier properties (WVTR < 1 g/m²/day), and electrical insulation (breakdown voltage > 300 V/μm). It protects underlying circuitry from environmental degradation and mechanical damage.

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