Overview
Through-silicon vias (TSVs) create vertical electrical connections through a silicon wafer or die, enabling the 3D-IC stacking and heterogeneous integration that 2D scaling can no longer deliver alone. GINECHIP's TSV process covers deep reactive-ion etch, dielectric liner deposition, barrier/seed metallization, and Cu or W via fill across via-first, via-middle, and via-last integration schemes.
Each TSV process is qualified with cross-sectional SEM void inspection, electrical continuity testing, and CTE-matched fill verification. We support via diameters from 2μm to 100μm with aspect ratios up to 20:1, on 100mm to 300mm wafers, under ISO 9001-certified process control.
Process Modules
Deep Reactive-Ion Etching (DRIE)
Bosch-process deep silicon etch defines high-aspect-ratio via openings with controlled sidewall angle and minimal scalloping, forming the foundation for reliable TSV interconnects.
Dielectric Liner
Thermal or PECVD oxide/nitride liners electrically isolate the copper via from the surrounding silicon, balancing conformality, breakdown strength, and thermal budget across via geometries.
Barrier & Seed Layer
PVD or ALD tantalum/TaN barrier prevents copper diffusion into silicon, while a sputtered copper seed layer enables uniform bottom-up electroplating in high-aspect-ratio vias.
Copper Electroplating
Additive-controlled bottom-up superfilling deposits void-free copper from the via bottom upward, followed by a post-plate anneal to relieve stress and stabilize grain structure.
CMP & Backside Finish
Chemical-mechanical polishing removes overburden copper with tightly controlled dishing and erosion, followed by backside reveal, cleaning, and optional Ni/Au finish for downstream assembly.
Process Options
Via-Middle Integration
TSVs are formed after front-end transistor fabrication but before back-end interconnect, enabling dense via arrays while remaining compatible with existing BEOL thermal budgets.
Via-Last Integration
TSVs are etched from the wafer backside after BEOL metallization is complete, avoiding any disruption to front-end or back-end process flows at the cost of via-to-pad alignment tolerance.
Process Flow
Wafer Preparation
Incoming wafers are inspected, cleaned, and patterned with a hard mask defining via locations and diameters.
Deep Silicon Etch
Bosch-process DRIE etches vias to target depth with controlled sidewall angle and scallop size.
Dielectric Liner
Thermal or PECVD oxide/nitride is deposited to electrically isolate the via sidewall from silicon.
Barrier & Seed
PVD or ALD barrier and copper seed layers are deposited to enable void-free electroplating.
Copper Fill
Bottom-up electroplating fills the via with void-free copper, followed by a stress-relief anneal.
CMP & Inspection
Overburden copper is polished back, and X-ray/acoustic inspection confirms fill integrity before backside processing.
Quality Assurance
| Parameter | Target | Method |
|---|---|---|
| Via Resistance | < 50 mΩ (typical, 10×100μm via) | 4-point Kelvin probe on test structures |
| Chain Yield | > 99.9% (1,000-via chain) | 4-point resistance continuity |
| Dielectric Breakdown Voltage | > 50V (for 200nm thermal SiO₂) | Ramped voltage I-V sweep |
| Leakage Current | < 1 nA at 5V (silicon-to-TSV) | I-V measurement, Si grounded, TSV biased |
| Cu Protrusion | < 100nm @ 400°C anneal | AFM / profilometry |
| Void Content | Zero voids > 1μm in fill | X-ray microscopy / acoustic microscopy |
| Scallop Depth | < 50nm (Bosch process) | SEM cross-section |
| Via Capacitance | 50–200 pF (dependent on geometry) | C-V measurement at 1 MHz |
Quality Note
Via Fill
Polyimide via filling creates planarized interlayer dielectrics with excellent gap-fill capability. The spin-on application fills high-aspect-ratio vias without voids, and the thermal curing process ensures homogeneous material properties throughout the filled structures.
Our via-fill polyimide process achieves aspect ratios up to 3:1 with void-free filling, as verified by cross-sectional SEM. The planarization capability reduces topography for subsequent lithography steps, improving CD uniformity across the wafer.
Photosensitive polyimide formulations enable direct patterning of via openings without separate photoresist processing. This reduces process steps by 30% while achieving via resolution down to 5μm.
Applications
3D-IC Stacking
Vertical die-to-die interconnects for high-bandwidth, low-latency communication between stacked logic and memory dies.
CMOS Image Sensors
Backside vias for compact camera modules, eliminating wire-bond loops and enabling smaller package footprints.
2.5D Interposers
Silicon interposers with TSV routing connect multiple chiplets on a single substrate for heterogeneous integration.
MEMS-CMOS Integration
Hermetic vertical interconnects between MEMS sensor wafers and CMOS ASIC wafers in wafer-level packages.
Barrier Technology
Polyimide serves as an excellent stress buffer layer between silicon substrates and subsequent metal or dielectric layers. Its low elastic modulus (~3 GPa) and high elongation (>30%) absorb thermal-mechanical stress during packaging and thermal cycling.
As a passivation layer, polyimide provides excellent chemical resistance, moisture barrier properties (WVTR < 1 g/m²/day), and electrical insulation (breakdown voltage > 300 V/μm). It protects underlying circuitry from environmental degradation and mechanical damage.
Ready to Get Started?
Contact our engineering team to discuss your specific requirements and receive a detailed quotation within 24 hours.