SOI Wafer (Silicon-On-Insulator)
Engineered three-layer substrates — device silicon on buried oxide on handle wafer. Smart Cut, BESOI, SIMOX, and ELTRAN technologies for RF-SOI, FD-SOI CMOS, MEMS sensors, silicon photonics, and power-management ICs. 200mm and 300mm diameters with custom BOX and device-layer specifications.
What is SOI?
Silicon-On-Insulator (SOI) is an engineered substrate technology in which a thin, single-crystal silicon device layer is electrically isolated from a bulk silicon handle wafer by a buried oxide (BOX) layer — typically thermal SiO₂. This three-layer architecture eliminates the parasitic junction capacitance inherent in bulk CMOS, delivering significant advantages in speed, power efficiency, noise isolation, radiation tolerance, and high-temperature operation.
SOI technology has evolved from a niche substrate for defense and aerospace in the 1990s to a mainstream platform powering over 1.5 billion RF front-end modules annually, with RF-SOI commanding more than 85% of the smartphone switch and antenna-tuner market. The emergence of FD-SOI at advanced CMOS nodes has further expanded SOI's reach into edge AI, automotive microcontrollers, and 5G infrastructure — all leveraging the unique ability to dynamically tune transistor threshold voltage via back-gate biasing.
At GINECHIP, we source SOI wafers manufactured through all four established methods — Smart Cut (Soitec), BESOI, SIMOX, and ELTRAN — across 200mm and 300mm diameters with custom device-layer and BOX specifications. Every lot is supplied with full metrology data: cross-sectional TEM, spectroscopic ellipsometry, AFM roughness, and SRP resistivity profiling.
SOI Material Stack Architecture
Monocrystalline silicon film where active devices are fabricated. Resistivity and doping tuned to your process requirements.
High-quality thermally-grown silicon dioxide providing electrical isolation, radiation hardness, and etch-stop precision for MEMS release.
Mechanical support substrate. Available in standard resistivity or High-Resistivity (>3 kΩ·cm) with optional Trap-Rich layer for enhanced RF performance.
SOI Manufacturing Technologies
Four distinct fabrication methods produce SOI substrates, each with unique trade-offs in device-layer quality, cost, and scalability. Our supply chain covers all four technologies so we can recommend the best match for your application, volume, and budget.
Smart Cut
Proprietary Soitec process using hydrogen implantation and wafer splitting
Implanted hydrogen forms a buried cleave plane; thermal activation splits the wafer. The donated device layer inherits the crystal quality of the donor wafer. The split donor can be reclaimed and reused, reducing cost. Dominant technology in the global SOI market (>90% share).
BESOI
Bonded and Etched-back SOI — direct wafer bonding with mechanical thinning
Two oxidized wafers are bonded face-to-face at room temperature, then annealed to strengthen the bond. The device wafer is ground and polished back to the target thickness. Ideal for thick device layers where Smart Cut cannot reach.
SIMOX
Separation by IMplantation of OXygen — high-dose oxygen implantation
High-dose oxygen ions are implanted into a silicon wafer; high-temperature annealing forms a stoichiometric SiO₂ layer below the surface. Produces the thinnest and most uniform BOX layers. Historically significant for radiation-hardened SOI CMOS.
ELTRAN
Epitaxial Layer TRANsfer — porous silicon lift-off process (Canon)
Epitaxial silicon grown on porous Si is bonded to an oxidized handle wafer. A water-jet splits the structure along the mechanically weak porous layer. The epitaxial device layer features exceptional crystal quality with low defect density.
Handle Wafer Options for RF Performance
The electrical properties of the handle wafer profoundly influence high-frequency device performance — especially for RF-SOI switches and 5G/mmWave LNAs where substrate coupling parasitics can dominate insertion loss and harmonic distortion.
Standard Resistivity
10–30 Ω·cm, p-type boron-doped. Lowest cost, suitable for DC and low-frequency applications where parasitic substrate coupling is not critical.
High-Resistivity (HR-Si)
>3 kΩ·cm, p-type. Reduces substrate-induced insertion loss and cross-talk. Minimum specification for 4G/LTE RF-SOI front-end switches.
Trap-Rich HR-Si
>3 kΩ·cm with polysilicon or amorphous-Si trap layer. Suppresses the parasitic surface conduction channel that degrades effective resistivity at high frequencies. Required for 5G sub-6GHz and mmWave.
Technical Specifications
| Parameter | Available Range / Values |
|---|---|
| Device Layer Thickness | 50nm – 100μm (tolerance ±5% or better) |
| Device Layer Resistivity | 0.001 – 10,000 Ω·cm (P-type / N-type) |
| Device Layer Orientation | 〈100〉, 〈111〉, 〈110〉 (off-cut on request) |
| BOX Thickness | 100nm – 2μm thermal SiO₂ (up to 4μm custom) |
| BOX Uniformity | ±1% within-wafer, ±2% wafer-to-wafer (Std Dev) |
| Handle Wafer Diameter | 200mm (8″), 300mm (12″) |
| Handle Wafer Type | Standard, High-Resistivity (>3kΩ·cm), Trap-Rich HR-Si |
| Manufacturing Method | Smart Cut (Soitec), BESOI, SIMOX, ELTRAN |
| TTV / Bow / Warp | As low as < 3μm TTV, < 10μm Bow, < 15μm Warp |
| Surface Roughness (RMS) | < 0.2nm (AFM, 1×1μm scan) — Epi-Ready |
| Particle Specification | ≤ 10 particles @ 0.2μm (SEMI M53 compliant) |
Applications & Market Segments
RF Front-End Modules
RF-SOI switches, LNAs, and antenna tuners for 4G/5G smartphones, WiFi 6E/7, and IoT connectivity. Low insertion loss and high linearity over 6 GHz.
FD-SOI CMOS
Fully Depleted SOI for ultra-low-power digital logic at 28nm, 22nm, and 18nm nodes. Back-bias capability enables dynamic Vt tuning for IoT and edge AI processors.
Power Management ICs
BCD-SOI technology for automotive, industrial, and consumer PMICs. High-voltage isolation up to 200V with reduced parasitic capacitance.
MEMS Sensors & Actuators
Precision MEMS structures using the device layer as a mechanical element. Accelerometers, gyroscopes, pressure sensors, micro-mirrors, and RF-MEMS resonators.
Silicon Photonics
SOI waveguides and photonic integrated circuits (PICs) for datacom transceivers, LIDAR beam steering, and quantum photonics. High-index-contrast optical confinement.
Radiation-Hardened Electronics
SOI substrates for space, aerospace, and nuclear applications. Inherent latch-up immunity and reduced single-event effects from the insulating BOX layer.
High-Temperature Electronics
SOI circuits operating above 225°C for downhole drilling, automotive engine compartments, and geothermal monitoring — where bulk CMOS fails.
Power SOI & LDMOS
High-voltage LDMOS transistors on SOI for base station power amplifiers, ENVELOPE tracking, and industrial motor drives. Superior isolation and thermal management.
Metrology & Quality Assurance
Every SOI wafer lot undergoes a rigorous multi-technique characterization protocol at our ISO 9001:2015 certified partner facilities. A full Certificate of Analysis (CoA) accompanies each shipment.
Need SOI Wafers for Your Process?
Specify your device-layer thickness, BOX thickness, handle wafer resistivity, diameter, and quantity — our SOI substrate specialists will provide a detailed quotation with metrology data and lead time within 24 hours.