Silicon Wafer Substrate
The foundational material for MEMS, CMOS, power devices, and photonics. Engineered to your exact resistivity, orientation, and surface specification.
Overview
Silicon wafers remain the dominant substrate for semiconductor device fabrication — accounting for over 90% of the global semiconductor substrate market. At GINECHIP, we source and distribute silicon substrates across every major grade, diameter, and specification, serving wafer fabs, MEMS foundries, R&D institutions, and packaging houses in more than 50 countries.
Whether your application demands prime-grade CZ wafers for volume CMOS production, ultra-flat FZ wafers for power devices, SOI substrates for RF-SOI switches, or cost-effective test-grade wafers for process qualification — our supply chain delivers consistent lot-to-lot quality with full material traceability.
Material Grades
Prime Grade
Highest quality CZ or FZ wafers with tightly controlled resistivity, oxygen/carbon content, and near-zero defect density. Used for device fabrication in production environments. SEMI M1-0302 compliant.
- EPD < 1/cm² (CZ), < 0.1/cm² (FZ)
- Oxygen: 12–18 ppma (ASTM F121)
- COP-free annealed wafers available
Test / Monitor Grade
Cost-optimized wafers for process monitoring, equipment qualification, and particle counting. Matching resistivity and type to your production line.
- EPD < 100/cm²
- Reliable for daily fab metrology
- Available with custom laser scribe marks
SOI (Silicon-On-Insulator)
Device-layer silicon bonded over buried oxide (BOX). Ideal for RF front-end modules, MEMS accelerometers, and high-temperature electronics.
- Device layer: 50nm–100μm
- BOX: 100nm–2μm thermal oxide
- Handle wafer: 200mm or 300mm
Mechanical / Dummy
Non-critical specification wafers for mechanical testing, cassette filling, thermal uniformity, and equipment setup. Significant cost savings versus prime.
- Loose resistivity & type
- Bulk purchase discounts available
- Also available: oxidized dummy wafers
Technical Specifications
| Parameter | Available Range / Values |
|---|---|
| Diameter | 100mm (4″), 150mm (6″), 200mm (8″), 300mm (12″) |
| Type / Dopant | P-type (Boron), N-type (Phosphorus, Arsenic, Antimony) |
| Resistivity | 0.001–10,000 Ω·cm (custom ranges available) |
| Orientation | 〈100〉, 〈111〉, 〈110〉 (off-cut angles available) |
| Thickness | 200μm–1000μm (standard SEMI specs ± custom) |
| Grade | Prime, Test, Monitor, Mechanical, Dummy, Reclaim |
| Polish | SSP (Single-Side), DSP (Double-Side), CMP-finished |
| Backside | Bright-etched, Lapped, Polysilicon, Oxide/Nitride layer |
| Flat/Notch | SEMI Std flats, Notch per SEMI M1 (custom alignment marks) |
| TTV / Bow / Warp | As low as < 2μm TTV, < 5μm Bow, < 10μm Warp |
| Particles | ≤ 10 particles @ 0.2μm (Class 1 cleanroom packaging) |
Surface Finishes & Backside Treatments
Frontside Polish
- CMP (Chemical-Mechanical Polish) — sub-nanometer RMS roughness for advanced lithography
- SSP (Single-Side Polished) — standard for most MEMS and CMOS processes
- DSP (Double-Side Polished) — required for double-side alignment photolithography
- Epi-Ready — surface prepared for epitaxial growth with < 5Å native oxide
Backside Options
- Bright-Etched — acid-etched for uniform appearance
- Lapped — mechanically ground for thickness control
- Polysilicon Backseal — gettering layer for heavy-metal contamination control
- Thermal Oxide / LPCVD Nitride — dielectric backside for etch-stop or isolation
- Custom Backside Film Stacks — oxide-nitride, ONO, or metal backside
Crystal Growth Methods
We supply substrates produced via the following ingot growth techniques:
CZ (Czochralski)
The most common method — pulling a single-crystal seed from molten silicon under controlled thermal conditions. Produces 200mm and 300mm wafers at competitive cost for high-volume manufacturing.
FZ (Float Zone)
Ultra-high purity silicon refined via zone melting. Characterized by extremely low oxygen (< 0.2 ppma) and carbon content. Essential for high-voltage IGBTs, RF power transistors, and radiation detectors.
MCZ (Magnetic CZ)
Applied magnetic field during CZ growth suppresses melt convection, reducing oxygen incorporation and improving resistivity uniformity. Preferred for CCD/CMOS image sensors and high-end analog ICs.
Applications
Quality & Certification
Every lot ships with a Certificate of Conformance including resistivity map, thickness profile (TTV/Bow/Warp), particle count, and crystallographic verification. Our supply chain operates under ISO 9001:2015 certified quality management with full SEMI Standards traceability.
Need Silicon Wafers for Your Process?
Tell us your diameter, type, resistivity, orientation, and quantity — our engineering team will respond with a competitive quote within 24 hours.