Silicon Wafer Substrate
siliconWaferSubstrate.desc
Overview
Silicon wafers remain the dominant substrate for semiconductor device fabrication — accounting for over 90% of the global semiconductor substrate market. At GINECHIP, we source and distribute silicon substrates across every major grade, diameter, and specification, serving wafer fabs, MEMS foundries, R&D institutions, and packaging houses in more than 50 countries.
Whether your application demands prime-grade CZ wafers for volume CMOS production, ultra-flat FZ wafers for power devices, SOI substrates for RF-SOI switches, or cost-effective test-grade wafers for process qualification — our supply chain delivers consistent lot-to-lot quality with full material traceability.
Silicon Wafer Product Categories
Select a category to explore detailed specifications, manufacturing methods, and request a quotation.
Prime Silicon Wafers
Device-grade CZ & FZ substrates. Sub-nanometer roughness, tight resistivity and thickness tolerances for CMOS, MEMS, and power devices.
Test / Monitor Wafers
Cost-optimized wafers for fab equipment qualification, process monitoring, and daily tool checks. Consistent electrical and mechanical properties.
Dummy / Mechanical Wafers
Lowest-cost non-production wafers for furnace fill, tool setup, thermal uniformity control, and mechanical handling qualification.
Reclaimed Wafers
Chemically-mechanically stripped and repolished wafers restored to near-prime quality. 30–60% cost savings with up to 5 reclaim cycles.
Ultra-Thin / Taiko Wafers
Wafers thinned to 20μm with Taiko ring process for 3D-IC stacking, power devices, BSI sensors, and advanced packaging.
FZ High-Resistivity Wafers
Float Zone silicon with >10 kΩ·cm resistivity and extreme purity. O₂/C < 5×10¹⁵. Preferred substrate for RFICs, photonics, and radiation detectors.
SOI Wafers
Silicon-on-Insulator substrates with device layer on buried oxide. Smart Cut, BESOI, SIMOX, ELTRAN. For RF-SOI, FD-SOI, MEMS, photonics.
Thermal Oxide on Silicon
High-quality thermally-grown SiO₂ layers 10nm–4μm. Dry, wet, and pyrogenic oxidation for gate oxides, diffusion masks, and etch-stop layers.
Nitride on Silicon (Si₃N₄)
LPCVD & PECVD Si₃N₄ films 20nm–2μm. Stoichiometric and low-stress formulations. Diffusion barrier, passivation, MEMS hard mask.
Silicon Epi Wafers
CVD homoepitaxial Si on Si. Custom doping and thickness 0.5–200μm. For CMOS sensors, power MOSFETs, IGBTs, and BiCMOS.
Crystal Growth Methods
We supply substrates produced via the following ingot growth techniques:
CZ (Czochralski)
The most common method — pulling a single-crystal seed from molten silicon under controlled thermal conditions. Produces 200mm and 300mm wafers at competitive cost for high-volume manufacturing.
FZ (Float Zone)
Ultra-high purity silicon refined via zone melting. Extremely low oxygen and carbon content. Essential for high-voltage IGBTs, RF power transistors, and radiation detectors.
MCZ (Magnetic CZ)
Applied magnetic field during CZ growth suppresses melt convection, reducing oxygen incorporation and improving resistivity uniformity. Preferred for CCD/CMOS image sensors and high-end analog ICs.
Technical Specifications
| Parameter | Available Range / Values |
|---|---|
| Diameter | 100mm (4″), 150mm (6″), 200mm (8″), 300mm (12″) |
| Type / Dopant | P-type (Boron), N-type (Phosphorus, Arsenic, Antimony) |
| Resistivity | 0.001–10,000 Ω·cm (custom ranges available) |
| Orientation | 〈100〉, 〈111〉, 〈110〉 (off-cut angles available) |
| Thickness | 200μm–1000μm (standard SEMI specs ± custom) |
| Polish | SSP (Single-Side), DSP (Double-Side), CMP-finished |
| Backside | Bright-etched, Lapped, Polysilicon, Oxide/Nitride layer |
| TTV / Bow / Warp | As low as < 2μm TTV, < 5μm Bow, < 10μm Warp |
| Particles | ≤ 10 particles @ 0.2μm (Class 1 cleanroom packaging) |
Surface Finishes & Backside Treatments
Frontside Polish
- CMP (Chemical-Mechanical Polish) — sub-nanometer RMS roughness for advanced lithography
- SSP (Single-Side Polished) — standard for most MEMS and CMOS processes
- DSP (Double-Side Polished) — required for double-side alignment photolithography
- Epi-Ready — surface prepared for epitaxial growth with < 5Å native oxide
Backside Options
- Bright-Etched — acid-etched for uniform appearance
- Lapped — mechanically ground for thickness control
- Polysilicon Backseal — gettering layer for heavy-metal contamination control
- Thermal Oxide / LPCVD Nitride — dielectric backside for etch-stop or isolation
- Custom Backside Film Stacks — oxide-nitride, ONO, or metal backside
Applications
Quality & Certification
Every lot ships with a Certificate of Conformance including resistivity map, thickness profile (TTV/Bow/Warp), particle count, and crystallographic verification. Our supply chain operates under ISO 9001:2015 certified quality management with full SEMI Standards traceability.
Need Silicon Wafers for Your Process?
Tell us your diameter, type, resistivity, orientation, and quantity — our engineering team will respond with a competitive quote within 24 hours.