Silicon Epi Wafers
Silicon wafers with precisely doped epitaxial layers grown via CVD — homoepitaxial Si on Si substrates. Custom resistivity, thickness (0.5μm–200μm), and doping profiles for CMOS image sensors, power MOSFETs, IGBTs, and BiCMOS processes. Layer thickness uniformity ±1% and doping uniformity ±3% across 300mm.
What Are Silicon Epitaxial Wafers?
Silicon epitaxial (epi) wafers are engineered substrates in which a single-crystal silicon layer — the epi layer — is grown by chemical vapor deposition (CVD) onto a polished silicon substrate wafer. The defining characteristic of homoepitaxy is that the deposited film replicates the crystal structure of the underlying substrate, enabling atomic-level registry across the interface. Unlike bulk wafers where resistivity and doping are uniform throughout, epitaxial wafers decouple the electrical properties of the active device region (epi layer) from the mechanical support substrate, enabling device designs impossible with bulk silicon alone.
GINECHIP provides epitaxial wafers with custom doping profiles: uniform (constant resistivity through the epi thickness), graded (resistivity transitions between two targets), multi-layer (distinct epi sub-layers with different doping), and buried-layer structures where a heavily doped region is created at the substrate/epi interface for vertical current collection. Thicknesses from 0.5μm (ultra-thin for advanced CMOS) to 200μm (power device drift regions) are produced using atmospheric or reduced-pressure CVD reactors, with tight ±1% thickness and ±3% doping uniformity across 300mm wafers.
Every epitaxial wafer lot is qualified with FTIR thickness mapping, mercury-probe or four-point-probe resistivity mapping, SRP (Spreading Resistance Profiling) for depth-resolved carrier concentration, SIMS for doping species verification, and XRD rocking-curve analysis to confirm single-crystal epitaxial quality. Full CoA provided with each shipment from ISO 9001:2015 certified partner facilities.
Epi Wafer Cross-Section Architecture
Device-quality single-crystal silicon grown by CVD epitaxy. Custom doping (As/P/B), resistivity 0.01–1000 Ω·cm. Defect density < 0.5 stacking faults/cm² with atomic-level interface registry to the substrate.
Abrupt or graded doping transition between substrate and epi layer. Transition width is controlled by reactor purge cycles and temperature ramp rates. Optional buried layer (n⁺ or p⁺) can be incorporated at this interface.
Polished single-crystal silicon substrate providing mechanical support and, in vertical devices, the low-resistance current path to the backside contact. Substrate doping is independently selected from the epi layer.
Epi Doping Profile Options
The doping profile through the epitaxial layer is the primary design parameter for epi wafers, determining the electrical characteristics of devices fabricated on the layer. GINECHIP offers four doping profile configurations to match your device requirements.
Uniform Doping
Constant resistivity throughout the epi layer thickness
Constant dopant flow during CVD deposition yields uniform resistivity. This is the most widely requested profile for power MOSFET drift regions, CMOS image sensor absorption layers, and analog IC epi layers.
Graded Doping
Resistivity transitions between two target values
Dopant gas flow is ramped during deposition to create a controlled resistivity gradient. Used in PIN diodes for optimized field profiles and in bipolar transistors for built-in drift fields reducing base transit time.
Multi-Layer
Two or more distinct epi sub-layers with different doping
Sequential deposition with dopant gas changes between layers enables complex vertical doping profiles. Essential for super-junction MOSFETs with alternating n/p pillars and IGBTs with field-stop and buffer layers.
Buried Layer
Heavily doped region at substrate/epi interface
Sub-collector buried layer formed by high-dose implant or diffusion into the substrate before epitaxy, followed by epi overgrowth. The low-resistance buried layer serves as the collector contact in vertical NPN bipolar transistors for BiCMOS and RF HBT processes.
CVD Epitaxy Process Chemistry
Silicon epitaxy is performed by chemical vapor deposition in which a silicon-containing precursor gas is thermally decomposed at the wafer surface, depositing silicon atoms that organize epitaxially onto the substrate lattice. The choice of precursor determines deposition rate, temperature window, and chlorine chemistry effects.
| Parameter | Silane (SiH₄) | Dichlorosilane (SiH₂Cl₂) | Trichlorosilane (SiHCl₃) |
|---|---|---|---|
| Deposition Temperature | 650–900°C | 1050–1150°C | 1100–1200°C |
| Pressure Regime | Atmospheric or reduced (10–100 Torr) | Atmospheric or reduced (40–760 Torr) | Atmospheric (760 Torr) |
| Deposition Rate | 0.2–2 μm/min (lower T) | 0.5–3 μm/min (moderate) | 1–5 μm/min (highest) |
| HCl By-product | None | Yes (2 HCl per Si deposited) | Yes (3 HCl per Si deposited) |
| Pattern Shift Sensitivity | High (no Cl etching) | Moderate (some Cl etching) | Low (Cl etching compensates) |
| Autodoping Suppression | Limited (no Cl scavenging) | Good (HCl etches surface dopants) | Excellent (high Cl scavenging) |
| Dopant Incorporation | High As/P/B incorporation efficiency | Moderate; controlled by Cl chemistry | Lower; strong Cl competition |
| Best For | Low-T selective epi, thin layers, SiGe | General-purpose epi, 100–200mm | Thick power device epi, 150–200mm |
Applications & Market Segments
CMOS Image Sensors (CIS)
High-resistivity p/p⁺ epitaxial wafers for backside-illuminated (BSI) CMOS image sensors. Thick, low-defect epi layers provide the photon absorption region with long carrier diffusion lengths and low dark current for high quantum efficiency.
Power MOSFETs & IGBTs
Thick n-type epi layers (10–150μm) on heavily-doped n⁺ substrates form the voltage-blocking drift region in vertical power MOSFETs, IGBTs, and super-junction devices. Epi resistivity directly determines breakdown voltage rating (BV<sub>DSS</sub>).
BiCMOS & RF Bipolar
Buried-layer epitaxy for BiCMOS processes: n⁺ sub-collector buried layer followed by n-type epi for the collector region. Enables high-f<sub>T</sub> SiGe HBTs with f<sub>max</sub> exceeding 300 GHz for mmWave RF front-ends.
Discrete Diodes & Rectifiers
Epitaxial Si wafers for PIN diodes, Schottky rectifiers, Zener diodes, and TVS protection devices. Custom epi resistivity and thickness profiles optimize forward voltage, reverse recovery, and breakdown characteristics.
MEMS on Epi
Epitaxial silicon as the structural layer in MEMS inertial sensors and pressure transducers. Epi-poly deposition on sacrificial oxide enables thick, low-stress polysilicon structural layers for surface micromachined accelerometers and gyroscopes.
Analog & Mixed-Signal ICs
High-resistivity epitaxial layers on low-resistivity substrates for analog ICs. The low-resistance substrate provides a solid ground plane while the high-resistivity epi reduces substrate coupling and crosstalk between analog blocks.
Radiation Detectors
Ultra-high-resistivity (>1 kΩ·cm) thick epitaxial wafers for silicon radiation detectors and particle physics sensors. Full depletion at moderate bias voltages enables high charge collection efficiency for X-ray, gamma, and charged-particle detection.
Advanced Memory Devices
Epitaxial silicon for DRAM cell capacitors, 3D NAND channel material, and emerging memory technologies (RRAM, MRAM). Defect-free epi surfaces enable high-quality gate dielectric growth and low leakage.
Technical Specifications
| Parameter | Available Range / Values |
|---|---|
| Epi Layer Thickness | 0.5μm – 200μm (standard); ultra-thin 50nm on request |
| Thickness Uniformity | ±1% within-wafer (Std Dev on 300mm); ±2% on 200mm |
| Doping Species | Arsenic (n-type), Phosphorus (n-type), Boron (p-type) |
| Resistivity Range | 0.01 – 1000 Ω·cm (custom doping; ±3% uniformity on 300mm) |
| Doping Profile Types | Uniform, graded, multi-layer, buried layer (sub-collector) |
| Transition Width (sub/epi) | < 5% of epi layer thickness (abrupt interface control) |
| Substrate Wafer Diameters | 100mm (4″), 150mm (6″), 200mm (8″), 300mm (12″) |
| Substrate Orientations | 〈100〉, 〈111〉, 〈110〉; off-cut to ±0.5° on request |
| Substrate Resistivity | 0.001 – 10,000 Ω·cm (CZ or FZ; n-type or p-type) |
| Deposition Method | CVD epitaxy (SiH₄, SiHCl₃, SiH₂Cl₂); atmospheric or reduced pressure |
| Epi Defect Density | < 0.5 stacking faults/cm²; < 10 dislocations/cm² (Class 100 cleanroom) |
| Backside Treatment | Polished, etched, or polysilicon back-seal for autodoping suppression |
Metrology & Quality Assurance
Epitaxial wafer quality is verified through a multi-technique characterization protocol addressing thickness, doping, crystal quality, and surface quality. Every lot is shipped with a comprehensive Certificate of Analysis.
Ready to Order Epitaxial Wafers?
Specify your epi layer thickness, resistivity (or doping concentration), doping type, profile type (uniform/graded/multi-layer/buried layer), substrate diameter and orientation, and quantity — our epitaxy specialists will provide a detailed quotation with metrology specifications within 24 hours.