Film & Coating Customization
Custom thin-film deposition and coating services — dielectric, metal, and multilayer stacks engineered to precise optical, electrical, and mechanical specifications.
Overview
Engineered thin-film deposition for semiconductor, MEMS, and photonics applications. From single-layer dielectrics to complex multilayer optical stacks, our deposition capabilities span thermal oxidation, PECVD, LPCVD, ALD, and PVD with rigorous thickness uniformity and composition control.
Every deposited film is qualified by spectroscopic ellipsometry for thickness and refractive index, 49-point mapping for uniformity, and wafer curvature measurement for stress characterization. Films are deposited on prime, test, and dummy-grade Si wafers — as well as SOI, glass, sapphire, and compound semiconductor substrates.
Dielectric Films
Comprehensive dielectric film deposition for gate oxides, inter-layer dielectrics, passivation, and hard masks. Thermal, CVD, and ALD options with thickness control from sub-nanometer to micron range.
| Parameter | Available Range / Values |
|---|---|
| Thermal SiO₂ (Dry) | 5nm–500nm, uniformity ±1%, RI 1.462, breakdown > 10 MV/cm |
| Thermal SiO₂ (Wet) | 50nm–3μm, uniformity ±2%, growth rate 5–10× faster than dry |
| PECVD SiO₂ | 100nm–5μm, uniformity ±3%, stress tunable (compressive or tensile) |
| LPCVD TEOS SiO₂ | 50nm–2μm, excellent step coverage, conformal > 95% |
| ALD Al₂O₃ | 5nm–100nm, uniformity ±0.5%, pinhole-free, high-k (εᵣ ≈ 9) |
| ALD HfO₂ | 2nm–50nm, EOT < 1nm, high-k (εᵣ ≈ 20–25) |
Lpcvd Nitride Title
Pecvd Nitride Title
Metal Films & Metallization
PVD sputtered and evaporated metal films for electrodes, interconnects, diffusion barriers, and seed layers. High-purity targets with controlled grain structure and low resistivity.
| Parameter | Available Range / Values |
|---|---|
| Al (Aluminum) | 100nm–5μm, PVD sputtered, ±1% Si or ±0.5% Cu doping available |
| Ti / TiN | Ti 10–50nm / TiN 20–200nm, PVD reactive sputtering, diffusion barrier |
| TiW (Titanium-Tungsten) | 50–300nm, PVD, superior diffusion barrier for Au metallization |
| Cr / Au | Cr 10–30nm (adhesion) + Au 50–500nm, evaporation or sputtering |
| Ni / NiV | 50nm–5μm, electroplated or sputtered, solder-wettable UBM |
| Pt (Platinum) | 50–300nm, PVD, high-temperature stable, inert electrode material |
Aluminum Metallization
Aluminum (Al) is the workhorse interconnect metal for CMOS, MEMS, and discrete devices. PVD sputtered with ±1% Si or ±0.5% Cu doping for electromigration resistance. Film stress can be tuned from slightly compressive to tensile by adjusting process pressure and power. Thickness range 100nm–5μm with < 5% 1σ uniformity. Post-deposition anneal at 400–450°C in forming gas is available for contact alloying and grain stabilization.
Gold Metallization
Gold (Au) metallization for high-reliability, inert-electrode, and wire-bonding applications. Cr/Au or Ti/Au stacks with 10–30nm adhesion layer and 50–500nm gold. Deposited by e-beam evaporation (lowest damage) or DC sputtering (better adhesion). Wire bond pull strength > 8 gf for 25μm Au wire on 200nm Au pads. Suitable for applications requiring oxidation-resistant, high-conductivity electrodes.
Under-Bump Metallization (UBM)
Under-bump metallization stacks for flip-chip and wafer-level packaging. Multilayer stacks typically include adhesion (Ti, Cr), diffusion barrier (Ni, NiV, TiW), and solder-wettable top layer (Au, Cu). All layers deposited in a single pump-down without breaking vacuum for clean interfaces. Electroplated Ni/Au UBM available up to 5μm thickness for power device applications. Compatible with SnAg, SnPb, and lead-free solder systems.
Multilayer Stacks
Engineered multilayer film stacks that combine dielectrics, metals, and semiconductors to achieve specific optical, electrical, or mechanical functions. Single-run deposition with uninterrupted vacuum for clean, low-defect interfaces.
ONO Stack (SiO₂ / Si₃N₄ / SiO₂)
Oxide-Nitride-Oxide inter-poly dielectric for non-volatile memory (flash, EEPROM) and DRAM capacitor dielectrics. Each layer is independently optimized for thickness, stress, and composition. The nitride layer provides high charge-trapping density, while the oxide layers ensure low leakage. EOT as low as 10nm with leakage current density < 10⁻⁷ A/cm² at 5 MV/cm. Total stack thickness 18–45nm, tunable by adjusting individual layer deposition times.
- SiO₂ / Si₃N₄ / SiO₂
- Total stack: 18–45nm
- EOT as low as 10nm
High-k / Metal Gate (HKMG) Stack
High-k dielectric with metal gate electrode stack for advanced CMOS gate development. IL SiO₂ (0.5–1nm chemical oxide) + ALD HfO₂ (2–5nm) + PVD TiN (5–20nm workfunction metal) + LPCVD poly-Si cap. EOT < 1nm achievable. Both n-type (TiAl, TaN with La capping) and p-type (TiN with Al capping) band-edge workfunction metals available. Post-deposition anneal at 500–1000°C in N₂ or forming gas for interface state passivation.
- IL SiO₂ + HfO₂ + TiN + Poly-Si
- EOT < 1nm achievable
- N-type and P-type band-edge workfunction
Anti-Reflective Coatings (ARC)
Bottom and top anti-reflective coatings for photolithography process control. BARC (SiON or organic, 50–100nm) suppresses substrate reflectivity and standing wave effects. TARC (Si-rich SiON, 30–80nm) matched to photoresist refractive index for optimal exposure uniformity. Reflectivity < 2% at target wavelength (i-line 365nm, KrF 248nm, ArF 193nm). Linewidth variation reduction of 30–50% compared to uncoated substrates.
- BARC: 50–100nm SiON or organic
- TARC: 30–80nm Si-rich SiON
- Optimized for i-line (365nm) and DUV (248nm)
MEMS Sacrificial & Structural Stacks
Sacrificial and structural layer stacks for surface micromachining. PSG or SiO₂ (0.5–5μm) as sacrificial layer with high etch selectivity in vapor HF or BOE. LPCVD poly-Si (0.5–10μm) as structural layer with controlled residual stress. Multilayer stacks with alternating sacrificial and structural layers for complex 3D MEMS structures. Sacrificial-to-structural etch selectivity > 1000:1 for clean, stiction-free release.
- PSG / SiO₂ sacrificial
- LPCVD poly-Si structural
- Vapor HF or BOE release compatible
Film Metrology & Characterization
Every deposited film undergoes comprehensive metrology before shipment. Thickness, refractive index (n & k), stress, composition, and surface roughness are measured and documented in the final quality report. Below is our standard characterization suite.
- Spectroscopic Ellipsometry — thickness and n/k to ±0.1nm (Woollam M-2000)
- 49-Point Thickness Mapping — within-wafer uniformity verification
- Wafer Curvature / Stress — Tencor FLX, full-wafer stress map
- XRR (X-Ray Reflectivity) — sub-nanometer thickness for ultra-thin films
- AFM Surface Roughness — Ra/RMS per 1×1μm and 10×10μm scans
- Four-Point Probe — sheet resistance for conductive films
- XPS / EDX — film composition and stoichiometry verification
- Optical Microscope Inspection — visual check for pinholes, particles, delamination
Applications
Quality & Certification
All film deposition is performed in ISO Class 5 (Class 100) cleanrooms with continuous particle monitoring. Each lot is accompanied by a Certificate of Conformance documenting thickness, uniformity, refractive index, film stress, and surface roughness. In-process SPC charts are maintained for every deposition tool, and all metrology equipment is calibrated to NIST-traceable standards. For R&D customers, detailed process recipes and characterization data are included to enable reproducible results.
Request Your Custom Film Stack
Tell us your target thickness, material, stress budget, and wafer specification. Our thin-film engineers will recommend the optimal deposition method and provide a detailed quote within 24 hours.