Pattern Customization
Custom lithography patterns on wafers — laser scribe marks, alignment marks, metrology targets, and dedicated test structures tailored to your process requirements.
Overview
Pattern customization adds functional or identification features to bare silicon, glass, or SOI wafers through photolithography and etching. Whether you need wafer-level laser scribe marks for traceability, alignment marks for your stepper tools, or custom metrology targets for process control — we can pattern your wafers to your exact specifications.
We deliver industry-leading pattern fidelity with full traceability — every patterned wafer includes a complete documentation package with wafer maps, CD-SEM reports, overlay accuracy data, and certificates of conformance per ISO 9001:2015 and SEMI standards.
Laser Scribe & Identification Marks
Permanent wafer identification and traceability marks applied by laser or lithography:
| Parameter | Available Range / Values |
|---|---|
| Mark Type | OCR alphanumeric, 2D Data Matrix, QR code, custom logo/graphic |
| Character Height | 0.3mm–3.0mm (SEMI T7 compliant) |
| Dot Matrix Density | 5×7, 7×9, 9×13, 11×15 (custom grids) |
| Mark Position | SEMI M1.15 standard zone, custom quadrant/edge placement |
| Marking Technology | Laser (soft-mark < 5μm depth, hard-mark 5–50μm depth) |
| OCR Readability | > 99.9% read rate (SEMI M12/M13 compliant) |
| Font Options | SEMI OCR standard, high-density, human-readable only, custom |
Soft Mark (Laser Scribe)
- OCR, 2D Data Matrix, QR code, alphanumeric text
- Applied to front-side, back-side, or wafer edge
- Mark depth: < 5μm per SEMI T7 soft mark standard
- SEMI T7, M12, and M13 compliant
- 2D code on wafer edge for minimal area consumption
Hard Mark (Deep Etch)
- Permanent marks surviving oxidation, diffusion, and etching
- Etched depth: 5–50μm for long-lifetime traceability
- Laser or DRIE-etched alphanumeric, 2D codes and custom patterns
- Readable by automated optical inspection (AOI) after multiple process steps
- Compatible with SEMI T7 and M12 standards for permanent wafer ID
Alignment & Registration Marks
Precision alignment and registration marks for lithography tools, wafer bonding equipment, and metrology systems.
| Parameter | Available Range / Values |
|---|---|
| Alignment Mark Type | Cross, chevron, box-in-box, Vernier scale, custom |
| Mark Depth / Height | 100nm–5μm (etched), 50nm–2μm (deposited contrast layer) |
| Placement Accuracy | ±0.5μm standard, ±0.1μm precision (stepper-aligned) |
| Mark Material | Etched Si, trench-refilled poly-Si, W-plug, TiN, Cr |
| Global Alignment Grid | 5-point, 9-point, full-contact exposure grid, custom |
| ASML / Nikon / Canon | Compatible mark designs for major scanner platforms |
Etched Alignment Marks
Permanent alignment marks etched into the wafer surface for stepper and scanner alignment across multiple process steps.
Deposited Metal Alignment Marks
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Metrology & CD Targets
Comprehensive CD, overlay, and film thickness measurement targets for process development and in-line metrology.
Every patterned wafer is verified for alignment mark accuracy and placement precision before shipment.
Flats & Notches
SEMI-standard flats and custom notches for wafer orientation identification, doping type indication, and automated tool compatibility.
| Parameter | Available Range / Values |
|---|---|
| Primary Flat | Per SEMI M1: {110} flat for 〈100〉, {110} flat for 〈111〉 |
| Notch | Per SEMI M1: {110} notch for 200mm+, {110} notch for 300mm |
| Custom Flat Angle | Any crystallographic direction (±0.1° tolerance) |
| Custom Notch Shape | Standard JIS/SEMI, custom depth/width, dual-notch |
| Secondary Flat | Per SEMI M1 for conductivity type identification |
| Edge Profile | SEMI standard, T-style, C-style, custom chamfer |
Why Custom Wafer Edges?
- Reduced edge chipping — custom edge profiles minimize particle generation during handling
- Improved tool compatibility — edge geometry optimized for specific wafer handling systems and cassettes
- Reduced wafer breakage — engineered edge profiles lower stress concentration at the wafer periphery
- SEMI standard compliance — all edge geometries conform to SEMI M1 and M13 dimensional specifications
Edge Profile Options
- Rounded (bullnose) — reduced edge chipping, preferred for automated handling
- Beveled — angled edge for reduced mechanical stress during bonding
- Polished edge — mirror finish, minimizes particle generation
- Ground edge — economical, suitable for non-critical applications
Die-Level Customization Services
Precision patterns applied at the die level across entire wafers for traceability, singulation, and multi-project integration.
Die Serialization
Unique die-level identification codes for traceability and automated sorting throughout the assembly process.
- OCR and 2D Data Matrix codes per die
- Die coordinates and wafer lot genealogy encoding
- Compatible with automated die bonders and pick-and-place
- Custom font, size, and placement per design rules
Custom Dicing Streets
Custom dicing street patterns for process development and specialized singulation methods.
- Etched dicing lane patterns for stealth dicing or plasma dicing development
- TEG (Test Element Group) placement within dicing streets
- Custom street width: 30–200μm
- Alignment to crystal orientation for preferential cleaving
Multi-Project Wafer (MPW) Frames
Multi-Project Wafer (MPW) frame layouts with reticle-level alignment, chip ID, and test structures for cost-shared prototyping.
- Custom reticle frames with chip ID and alignment marks
- Reticle-to-reticle alignment verification structures
- Test structures and process control monitors (PCM) per reticle
- Compatible with GDSII and OASIS layout formats
Backside Alignment Marks
IR-transparent alignment marks on the backside for MEMS, power device, and 3D-IC double-side alignment.
- Front-to-back overlay accuracy: ±0.5μm
- IR camera-compatible alignment target designs
- Compatible with EVG, SUSS, and AML wafer bonders
- Patterned on silicon, glass, and SOI substrates
Metrology & Process Control Structures
Built-in metrology targets for process characterization, SPC, and equipment qualification — patterned directly on your production or monitor wafers.
- Sheet Resistance Monitors: Van der Pauw crosses, Greek crosses, and bridge resistors for Rs and contact resistance (Rc)
- Thickness Monitors: Step-height structures, ellipsometry pads, and profilometry trenches for film thickness verification
- Stress & Strain: Cantilever arrays, ring-and-beam structures, and buckling beam arrays for thin-film stress measurement
- Misalignment Monitors: Vernier structures, overlapping comb patterns for X/Y alignment error quantification with sub-100nm resolution
- Etch Rate Monitors: Depth markers, buried etch-stop indicators, and multi-depth calibration structures
- Electrical Test: Kelvin contact resistance structures, isolation test patterns, and breakdown voltage test structures
- Defect Detection: Intentional defect arrays of known size and location for inspection tool qualification and sensitivity verification
- Process Control Monitors (PCM): Complete PCM drop-in modules including transistors, capacitors, resistors, and diodes for wafer-level process monitoring
Applications
Quality & Certification
All patterned wafers are fabricated in ISO 9001:2015 certified facilities. Every wafer undergoes automated optical inspection (AOI), CD-SEM verification for critical dimensions, and overlay metrology for alignment accuracy. Full documentation including wafer maps, measurement reports, and certificates of conformance is provided with each shipment, ensuring complete traceability from pattern design to final delivery.
Need Custom Patterns on Your Wafers?
Tell us your pattern requirements — mark type, layout file (GDSII/DXF), substrate, and quantity — and we'll provide a detailed quotation within 24 hours.