Sapphire (Al₂O₃) Substrates
Single-crystal sapphire (Al₂O₃) wafer substrates for LED epitaxy, SOS technology, optical windows, and harsh-environment sensors. Available in C-plane, R-plane, and A-plane orientations from 2″ to 8″ diameters.
Single-Crystal Sapphire (α-Al₂O₃) Wafer Substrates
Single-crystal sapphire — the trigonal α-phase of aluminum oxide (Al₂O₃), also known as corundum — is the second-hardest natural material after diamond (9 on the Mohs scale) and combines extreme thermal stability (melting point 2,040°C) with broadband optical transparency from 150nm in the UV to 5,500nm in the mid-IR. These properties, together with its chemical inertness and high electrical resistivity, make sapphire an irreplaceable substrate material for III-nitride optoelectronics, silicon-on-sapphire (SOS) CMOS, high-temperature sensors, and scratch-resistant optical windows.
The global sapphire substrate market is dominated by the LED industry, where C-plane (0001) sapphire wafers serve as the epitaxial growth template for GaN-based blue and green LEDs. Over 90% of all commercial GaN LEDs — by wafer area — are manufactured on sapphire substrates, with annual demand exceeding 50 million 4″-equivalent wafers. The transition to 6″ and 8″ diameters in LED fabs has been driven by the economics of MOCVD reactor throughput, with 6″ now the mainstream diameter for high-volume LED manufacturing and 8″ entering production at leading epitaxy foundries.
At GINECHIP, we supply single-crystal sapphire substrates in C-plane, R-plane, A-plane, and M-plane orientations across diameters from 2″ to 8″. Surface finishes include SSP, DSP, and epi-ready CMP with RMS roughness below 2Å. Patterned sapphire substrates (PSS) with custom photonic crystal geometries are available for LED light extraction enhancement. Every lot is accompanied by a full Certificate of Analysis documenting orientation, rocking curve FWHM, EPD, TTV/bow/warp, surface roughness, and transmission spectra.
Crystal Growth Methods: Kyropoulos vs EFG vs HEM
The choice of sapphire crystal growth method determines the maximum boule size, achievable crystal quality (dislocation density), available crystallographic orientations, and ultimately the cost and performance of the resulting wafer substrates.
Kyropoulos (KY)
Melt-growth in W/Mo crucible — industry workhorse for LEDs
A seed crystal is lowered into an Al₂O₃ melt contained in a tungsten or molybdenum crucible under a controlled argon/helium atmosphere at ~2,050°C. Slow cooling over several days produces boules up to 300mm in diameter and 100kg in weight — the largest commercially available sapphire crystals. Reduced thermal gradients minimize dislocation density, making KY the preferred method for large-diameter C-plane substrates for LED epitaxy.
Edge-Defined Film-Fed (EFG)
Capillary-fed die growth — minimum waste, near-net shape
Sapphire melt is drawn through a die by capillary action, forming ribbons, tubes, or rods with cross-sections close to the final product shape. EFG-grown sapphire requires minimal core-drilling and slicing to produce wafers, reducing material waste and cost. Dominant for specialty shapes, R-plane substrates for SOS, and small-diameter wafers. Slightly higher dislocation density than KY-grown material.
Heat Exchanger Method (HEM)
Directional solidification on helium heat exchanger — lowest defect density
A helium-cooled heat exchanger at the crucible base extracts heat directionally, promoting controlled solidification from a single seed crystal placed on the heat exchanger. The resulting boule exhibits the lowest dislocation density (EPD < 10³/cm²) and minimal residual stress of any commercial sapphire growth method. Preferred for ultra-high-quality optical windows, armor-grade sapphire, and demanding laser applications where bulk scatter must be minimized.
Crystal Orientation Selection Guide
Sapphire is optically and mechanically anisotropic — its properties vary with crystallographic direction. The correct substrate orientation must be selected based on the epitaxial material system, device architecture, and processing requirements.
C-plane (0001)
The dominant orientation for GaN epitaxy. The six-fold symmetry of the (0001) basal plane promotes high-quality wurtzite GaN growth with the c-axis normal to the substrate surface. Used for > 90% of commercial LEDs, laser diodes, and GaN HEMTs.
R-plane (1-102)
The preferred orientation for silicon-on-sapphire (SOS) epitaxy. The R-plane facilitates growth of (100)-oriented silicon films with low defect density, enabling radiation-hard CMOS circuits for space and defense applications.
A-plane (11-20)
Used for non-polar and semi-polar GaN growth where the absence of polarization-induced electric fields along the growth direction improves the radiative recombination efficiency in green and longer-wavelength LEDs. Also used for microwave acoustic devices.
Patterned Sapphire Substrates (PSS) for LED Light Extraction
Patterned Sapphire Substrates (PSS) represent one of the most impactful innovations in solid-state lighting manufacturing. The large refractive index contrast between GaN (n ≈ 2.4) and sapphire (n ≈ 1.77) causes a significant fraction of photons generated in the LED active region to be trapped in waveguiding modes within the high-index GaN epilayers — ultimately absorbed as heat rather than emitted as useful light.
By photolithographically patterning the sapphire surface with periodic arrays of hemispheres, cones, pyramids, or photonic-crystal structures at micron to sub-micron pitch prior to epitaxial growth, the otherwise planar GaN-sapphire interface is transformed into a distributed Bragg reflector / scattering layer. Angled reflection and diffraction of waveguided photons into escape-cone trajectories increases light extraction efficiency (LEE) by 30–60% compared to planar substrates.
GINECHIP supplies PSS wafers with pattern geometries optimized for specific LED wavelength and chip architectures: micro-cone arrays (pitch 1–5μm, height 1–2μm) for standard blue LEDs; nano-patterned arrays (pitch 300–800nm) via nanoimprint lithography (NIL) for enhanced light extraction in micro-LED displays and vertical-cavity surface-emitting devices; and photonic quasi-crystal patterns for broadband angular emission control. Both dry-etched (ICP-RIE with BCl₃/Cl₂ chemistry) and wet-etched (H₃PO₄/H₂SO₄ at 270–300°C) patterning routes are available.
Silicon-on-Sapphire (SOS) Technology
Silicon-on-Sapphire technology — the heteroepitaxial growth of (100)-oriented silicon films on R-plane sapphire substrates via CVD at ~950–1,000°C using silane (SiH₄) — produces CMOS transistor channels isolated from the substrate by a buried insulating layer that is intrinsic to the material structure. This built-in isolation eliminates two of the most persistent problems in bulk silicon CMOS: latch-up (parasitic thyristor triggering between adjacent n- and p-channel transistors) and single-event latch-up (SEL) from ionizing radiation in space environments.
SOS CMOS circuits routinely achieve total ionizing dose (TID) tolerance exceeding 1 Mrad(Si) and single-event upset (SEU) immunity far surpassing that of bulk or SOI CMOS, making SOS the technology of choice for satellite communications, deep-space probes, nuclear instrumentation, and military avionics where radiation hardness is a non-negotiable requirement. The sapphire substrate additionally reduces parasitic source/drain-to-substrate capacitance, enabling higher-speed analog and RF performance for a given technology node.
Technical Specifications
| Parameter | Available Range / Values |
|---|---|
| Material | Single-crystal α-Al₂O₃ (Sapphire), various grades |
| Crystal Orientation | C-plane (0001), R-plane (1-102), A-plane (11-20), M-plane (10-10) |
| Diameter | 2″ (50.8mm), 3″ (76.2mm), 4″ (100mm), 6″ (150mm), 8″ (200mm) |
| Thickness | 330μm, 430μm, 650μm, 1,000μm standard |
| Surface Polish | SSP, DSP, Epi-Ready CMP, RMS < 2Å |
| TTV | ≤ 5μm |
| Bow / Warp | Bow ≤ 10μm, Warp ≤ 15μm for 4″ diameter |
| EPD (Etch Pit Density) | < 5 × 10³/cm² |
| Hardness | 9 Mohs, 2,000 kg/mm² Knoop |
| Thermal Conductivity | 40 W/m·K @ 300K |
| CTE | 5.0–6.6 × 10⁻⁶/K (anisotropic, orientation-dependent) |
| Melting Point | 2,040°C |
| Bandgap | 9.9 eV (wide-bandgap optical insulator) |
| Refractive Index | nₒ = 1.768, nₑ = 1.760 @ 633nm |
| Transmission Range | 150nm–5,500nm (UV-grade: 85% @ 250nm) |
| Miscut Tolerance | ±0.2° standard, ±0.05° precision |
| Packaging | Class 100 cleanroom, vacuum-sealed single-wafer cassette |
Applications & Market Segments
LED Epitaxy (GaN-on-Sapphire)
C-plane sapphire is the dominant substrate for gallium nitride (GaN) epitaxy in blue, green, and white LEDs. The 16% lattice mismatch is accommodated through low-temperature GaN or AlN buffer layers. Over 90% of all commercial GaN LEDs are grown on sapphire substrates, driving a multi-billion-unit annual wafer demand for solid-state lighting, displays, and automotive headlamps.
Laser Diodes & VCSELs
Sapphire substrates support GaN-based violet (405nm) and blue (450nm) laser diodes for Blu-ray optical storage, laser projectors, and high-power industrial lasers. The material's high thermal conductivity (40 W/m·K) aids heat extraction from the active region, critical for CW laser operation at watt-level output powers.
SOS (Silicon-on-Sapphire) Technology
R-plane sapphire wafers serve as the insulating substrate for epitaxial silicon layers in radiation-hardened CMOS circuits for space, military, and high-reliability applications. The insulating sapphire substrate eliminates latch-up, reduces parasitic capacitance, and provides total-dose radiation tolerance exceeding 1 Mrad(Si), far surpassing bulk silicon CMOS.
Patterned Sapphire Substrates (PSS)
Photolithographically patterned sapphire — with periodic hemisphere, cone, or pyramid arrays at micron or sub-micron pitch — enhances GaN LED light extraction efficiency by 30–60% through angled reflection and scattering of waveguided photons. PSS has become the de-facto standard substrate for high-brightness LED manufacturing at all major epitaxy foundries.
RF & Microwave ICs
High-resistivity silicon epitaxially grown on sapphire (HR-Si-on-Sapphire) provides low-loss RF substrates for switches, LNAs, and power amplifiers in handsets and base-station front-end modules. The insulating sapphire handle eliminates substrate eddy currents and capacitive coupling that degrade Q-factor and isolation in bulk CMOS RFICs.
Optical Windows & Armor
Sapphire's extreme hardness (9 Mohs), broad transparency (150nm–5,500nm), and chemical inertness make it the material of choice for scratch-resistant watch crystals, bar-code scanner windows, hypersonic missile domes, and transparent armor. HEM-grown boules provide the low-scatter optical quality required for multispectral sensor windows.
Metrology & Quality Assurance
Every sapphire substrate lot undergoes a rigorous multi-technique characterization protocol at ISO 9001:2015 certified facilities. Crystal quality is verified by HRXRD and EPD measurement; surface quality by AFM and laser particle scanning; and optical properties by spectrophotometry from UV through IR. A complete Certificate of Analysis accompanies each shipment.
Need Sapphire Substrates for Your LED or SOS Process?
Specify your orientation (C/R/A/M-plane), diameter (2″–8″), surface finish (SSP/DSP/Epi-Ready CMP), PSS requirements, and quantity — our sapphire substrate specialists will provide a detailed quotation with XRD and AFM data within 24 hours.