Photolithography
Precision wafer patterning from R&D prototyping to pilot production. Contact, proximity, projection stepper, laser direct write, and nanoimprint lithography — the right tool for every resolution and throughput requirement.
Overview
Photolithography is the fundamental patterning process that defines every feature in semiconductor and MEMS devices — transferring design layouts from mask (or digital file) to photoresist on the wafer surface. At GINECHIP, we operate a multi-technology lithography bay spanning five distinct exposure methods, enabling us to select the optimal balance of resolution, throughput, and cost for each project.
From high-resolution i-line projection steppers (0.35μm CD) for production-grade IC and photonics devices, to laser direct write systems for rapid maskless prototyping, to nanoimprint lithography for sub-50nm periodic structures — our lithography services are backed by full resist processing (coat, bake, develop), CD-SEM metrology, and overlay registration measurement.
Lithography Technologies
Contact Lithography
The photomask is placed in direct physical contact with the photoresist-coated wafer during UV exposure. Achieves the highest resolution among non-projection methods due to near-field diffraction effects. Ideal for R&D, prototyping, and low-volume production where 1–2μm feature sizes are sufficient.
Proximity Lithography
The mask is held a small distance (10–50μm) above the wafer surface during exposure. Eliminates mask damage and contamination issues inherent to contact mode. Suitable for applications where resolution requirements are relaxed (3–5μm) but mask lifetime is critical.
Projection Lithography
A reduction lens system projects the mask pattern onto the wafer at typically 4× or 5× reduction. This is the dominant production lithography method, offering superior resolution, depth of focus, and mask lifetime. Our stepper/scanner systems handle 200mm wafers with i-line (365nm) sources.
Laser Direct Write
Maskless lithography using a focused laser beam to directly expose patterns onto photoresist. Eliminates the need for physical masks — ideal for rapid prototyping, small-batch production, and designs requiring frequent revisions. Sub-micron resolution achievable.
Nanoimprint Lithography (NIL)
Mechanical patterning technique where a nanostructured stamp is pressed into a UV-curable or thermoplastic resist. Enables sub-100nm features at low cost without the diffraction limits of optical lithography. Excellent for photonic crystals, gratings, and nanofluidic channels.
Photoresist Portfolio
Positive Photoresists
Exposed regions become soluble and are removed during development. Higher resolution than negative resists. Common for IC fabrication: DNQ/novolac (i-line), chemically amplified resists (KrF, ArF).
Negative Photoresists
Exposed regions cross-link and become insoluble; unexposed regions are developed away. Superior adhesion and chemical resistance. SU-8 is the dominant negative resist for MEMS and microfluidics (aspect ratios > 20:1).
Image-Reversal Resists
Positive resist processed with an amine bake step to invert tone to negative. Produces re-entrant (undercut) profiles ideal for metal lift-off processes in GaAs/InP device fabrication.
Thick Resists
Positive and negative resists for coating thicknesses from 10μm to >200μm. SU-8 (negative) and AZ 9260 (positive) for electroplating molds, microfluidic channels, and MEMS structural layers.
Process Capabilities
| Process Parameter | Capability |
|---|---|
| Minimum Feature Size (CD) | 0.35μm (i-line stepper); 0.5μm (contact); 0.6μm (direct write); 50nm (NIL) |
| Overlay Registration | < 50nm (stepper); < 1μm (contact aligner) |
| Alignment Modes | Top-side, bottom-side, infrared backside, double-side |
| Resist Thickness Range | 0.1μm (thin imaging) to 200μm+ (SU-8 MEMS) |
| Development Methods | Immersion, spray, puddle; TMAH and solvent-based developers |
| Wafer Sizes | Fragments, 100mm, 150mm, 200mm, 300mm |
| Substrate Types | Si, SOI, glass (fused silica, borosilicate), GaAs, InP, SiC, sapphire |
| Mask Data Formats | GDSII, OASIS, DXF, CIF, Gerber |
Typical Applications
Cantilevers, membranes, comb-drive actuators, and inertial sensor structures defined with 1–5μm resolution contact/proximity lithography on silicon and SOI wafers.
SU-8 master molds for PDMS casting, channel networks, and reaction chambers. Thick resist processing (50–200μm) with vertical sidewalls for precise fluidic structures.
Ridge waveguides, grating couplers, and ring resonators patterned via i-line stepper or e-beam. Nanoimprint lithography for photonic crystal arrays and sub-wavelength gratings.
Thick metal lift-off patterns (Al, Au, Ni) for power transistor source/drain contacts and gate fingers. Image-reversal resist for controlled undercut profiles.
Through-silicon via etch mask definition with resolution down to 5μm. DRIE hard mask (SiO₂/Al) patterning for high-aspect-ratio silicon etching.
Maskless laser direct write for rapid design iteration. No mask fabrication cost or lead time — from GDSII layout to patterned wafer in hours.
Mask Design & Fabrication Support
We provide full mask design review and fabrication coordination. Our engineers verify your GDSII layout for design rule compliance, recommend optical proximity correction (OPC) where needed, and coordinate with mask shops for 5″ and 7″ chrome-on-glass reticles. For laser direct write and nanoimprint processes, no physical mask is required — accelerating your design-to-wafer cycle time from weeks to days.
Metrology & Inspection
Every patterned wafer undergoes critical dimension measurement (CD-SEM for sub-micron features, optical microscopy for ≥1μm), overlay registration verification, resist thickness measurement (spectroscopic reflectometry), and visual defect inspection. Full CD uniformity maps and registration vector plots are included in the process report.
Quality Assurance
Lithography is performed in ISO Class 5 (Class 100) cleanroom conditions with temperature and humidity control (±0.1°C, ±1% RH) to ensure resist coating uniformity and CD stability. All processes are run with established standard operating procedures (SOPs), and each lot includes a comprehensive process traveler documenting every step.
Need Precision Wafer Patterning?
Share your GDSII layout, target feature size, wafer specifications, and quantity — our lithography engineers will recommend the optimal technology and provide a detailed quotation within 24 hours.