Wafer Bumping UBM
Solder bump, copper pillar, and gold bump with full UBM stack support — SnAg, SAC, and AuSn alloys.
Overview
Wafer bumping is the critical interconnect technology enabling flip-chip assembly, 3D stacking, and wafer-level packaging. Bumps replace traditional wire bonds, offering shorter electrical paths, lower inductance, higher I/O density, and better thermal performance. GINECHIP delivers production-grade wafer bumping across multiple metallurgies.
Our wafer bumping services encompass solder bumps, Cu pillar, Au stud, micro-bumps, and C4 bumps with full UBM (Under-Bump Metallization) stacks. We support pitches from 130μm down to 10μm for 200mm and 300mm wafers, with lead-free (RoHS) and high-lead options.
Bumping Technologies
Solder Bump (SnAg/Cu, SnAg, SAC305)
Electroplated solder bumps on Cu UBM. Pitch 130–250μm. Bump height 50–120μm. Lead-free SAC305 and SnAg compositions. For standard flip-chip assembly via mass reflow. High throughput. 200mm and 300mm wafers. RoHS compliant.
Cu Pillar Bump
Electroplated Cu pillar (20–60μm height) with SnAg solder cap (10–30μm). Pitch 40–80μm. Superior current-carrying and thermal conductivity. Fine-pitch flip-chip and 3D stacking. No solder bridging at fine pitch. 200mm and 300mm.
Au Stud Bump
Thermosonic wire-bonded Au stud bumps. Pitch > 60μm. Bump diameter 40–80μm. For optoelectronics, LED, and GaAs device assembly. No UBM required on Au pads. Process temperature < 150°C. Cost-effective for low-volume and prototyping.
Micro-Bump (Cu/SnAg, 10–55μm Pitch)
Ultra-fine-pitch Cu/SnAg micro-bumps for 3D-IC and die-to-wafer stacking. Pitch 10–55μm. Bump diameter 5–25μm. Precision electroplating with < ±1μm height uniformity. Compatible with thermocompression bonding. For HBM, chiplet integration, and interposer stacking.
UBM Stack Options
Under-Bump Metallization provides the adhesion, diffusion barrier, and solder-wetting layers required for reliable wafer bumping. We offer a range of UBM stacks optimized for different solder types, pitch requirements, and reliability profiles.
Ti/Cu Sputtered Seed Layer
Sputtered Ti adhesion layer (500Å–1000Å) with Cu seed (3000Å–8000Å) for electroplating-based bump and RDL formation. Low contact resistance. Excellent adhesion to SiO₂, SiN, and polyimide passivation. Standard seed layer for Cu pillar and solder bump processes. 200mm and 300mm wafers.
Ti/Ni/Cu Barrier Stack
Ti adhesion, Ni diffusion barrier, and Cu seed layer stack blocks Sn-Cu intermetallic growth at the UBM interface. Ni thickness 0.5–3μm. Extends bump reliability under thermal cycling and electromigration stress. Preferred for high-current and high-temperature applications.
Cr/Cu/Au Stack
Cr adhesion layer (200Å–500Å) with Cu (1–3μm) and Au (0.3–1μm) cap layers. Supports Au stud and Au ball bumping without additional plating. Corrosion-resistant, fluxless process for RF, MEMS, and optoelectronic device assembly.
TiW/Au Stack
Sputtered TiW barrier (1500Å–3000Å) with Au cap (0.5–2μm) resists diffusion at elevated operating temperatures. Standard UBM for GaAs and compound semiconductor devices requiring wire-bondable, oxidation-resistant contact pads.
Electroless Ni/Au (ENIG)
Electroless Ni (3–8μm) with immersion Au flash (0.05–0.15μm) deposits selectively on exposed Al or Cu bond pads without sputtering or photolithography. Lower equipment cost route for solder ball and stud bump UBM. High-volume, cost-sensitive production.
Al/NiV/Cu Stack
Sputtered NiV barrier (0.3–0.8μm) with Cu cap (1–5μm) applied directly over Al bond pads — the standard foundry-compatible UBM for flip-chip bumping without additional under-metal etch or pad-opening steps. Widely used for solder bump and Cu pillar on Al I/O.
Bonding Process Flow
Incoming Prep
Incoming Inspection & Surface Prep: Verify wafer quality and clean surfaces.
UBM Deposition
UBM Deposition: Sputter-deposit adhesion, diffusion-barrier, and wetting layers.
Lithography Patterning
Lithography Patterning: Coat photoresist, then expose and develop the UBM/bump pattern.
Bump Formation
Bump Formation: Electroplate solder or Cu pillar, strip resist, etch UBM.
Reflow & Inspection
Reflow & Inspection: Solder reflow, AOI inspection, electrical test.
Typical Applications
Cu pillar and solder bump flip-chip interconnects for CPUs, GPUs, FPGAs, and high-speed SerDes. Low inductance (< 0.1nH) and resistance path. Improved power delivery and signal integrity vs wire bond.
Ultra-fine-pitch (10–40μm) Cu/SnAg micro-bumps for HBM die-to-die and die-to-wafer stacking. Through-silicon via (TSV) compatible. Ultra-thin die handling (< 50μm). Thermocompression bonding at < 280°C.
Fine-pitch solder bumps and Cu pillars for CMOS image sensor (CIS) flip-chip assembly. Low-temperature bonding for backside-illuminated (BSI) sensors. High interconnect density for large-format sensors.
Au stud bumps and Cu pillars for RFIC, mmWave PA/LNA, and antenna-in-package. Low parasitic inductance for > 20GHz applications. Au-Au thermocompression bonding for lowest loss. GaAs and GaN-on-SiC compatible.
Au stud bumps for LED flip-chip and micro-LED display assembly. High thermal conductivity for heat dissipation. Fine-pitch capability for high-resolution displays. GaN-on-sapphire and GaAs compatible.
Reliability Testing
Environmental reliability testing includes temperature cycling, HAST, high-temperature storage, and mechanical shock per MIL-STD and JEDEC standards. Bonded wafer pairs are qualified for your application-specific environmental conditions.
Quality Assurance
Our metrology laboratory maintains ISO 17025 accreditation with NIST-traceable reference standards. All measurement equipment undergoes daily calibration verification with certified reference wafers, and our measurement uncertainty is documented for each parameter type.
Need Wafer Bumping Services?
Specify your bump type, pitch, UBM requirements, and wafer specifications — our team will respond with a detailed quotation within 24 hours.