Substrates
MEMS Process
Reprocessing
Accessories
Applications & Resources
Shop About
Solder · Cu Pillar · Au StudStat Bump Tech
10μm–400μmPitch Range
100mm–300mmWafer Diameter
6 UBM StacksStat Ubm Stacks

Overview

Wafer bumping is the critical interconnect technology enabling flip-chip assembly, 3D stacking, and wafer-level packaging. Bumps replace traditional wire bonds, offering shorter electrical paths, lower inductance, higher I/O density, and better thermal performance. GINECHIP delivers production-grade wafer bumping across multiple metallurgies.

Our wafer bumping services encompass solder bumps, Cu pillar, Au stud, micro-bumps, and C4 bumps with full UBM (Under-Bump Metallization) stacks. We support pitches from 130μm down to 10μm for 200mm and 300mm wafers, with lead-free (RoHS) and high-lead options.

Bumping Technologies

Solder Bump (SnAg/Cu, SnAg, SAC305)

Electroplated solder bumps on Cu UBM. Pitch 130–250μm. Bump height 50–120μm. Lead-free SAC305 and SnAg compositions. For standard flip-chip assembly via mass reflow. High throughput. 200mm and 300mm wafers. RoHS compliant.

SnAg (SAC305, SAC405)SnAgCu (LF solder)AuSn (eutectic, 80/20)SnPb (for MIL/aerospace)Pitch: 60μm–400μmBump height: 15μm–100μm

Cu Pillar Bump

Electroplated Cu pillar (20–60μm height) with SnAg solder cap (10–30μm). Pitch 40–80μm. Superior current-carrying and thermal conductivity. Fine-pitch flip-chip and 3D stacking. No solder bridging at fine pitch. 200mm and 300mm.

Cu height: 10μm–80μmSolder cap: SnAg, SACPitch: 20μm–80μmAR up to 5:1Electromigration: 10× better vs solderNi barrier layer option

Au Stud Bump

Thermosonic wire-bonded Au stud bumps. Pitch > 60μm. Bump diameter 40–80μm. For optoelectronics, LED, and GaAs device assembly. No UBM required on Au pads. Process temperature < 150°C. Cost-effective for low-volume and prototyping.

Au (99.99% purity)Diameter: 25μm–80μmHeight: 15μm–50μmFluxless — clean processCompliant interconnectIndividual die or full wafer

Micro-Bump (Cu/SnAg, 10–55μm Pitch)

Ultra-fine-pitch Cu/SnAg micro-bumps for 3D-IC and die-to-wafer stacking. Pitch 10–55μm. Bump diameter 5–25μm. Precision electroplating with < ±1μm height uniformity. Compatible with thermocompression bonding. For HBM, chiplet integration, and interposer stacking.

Pitch: 10μm–55μmCu/Ni/SnAg micro-bumpsDiameter: 5μm–25μmHybrid bonding compatibleMass reflow or TCB bonding300mm wafer compatible

UBM Stack Options

Under-Bump Metallization provides the adhesion, diffusion barrier, and solder-wetting layers required for reliable wafer bumping. We offer a range of UBM stacks optimized for different solder types, pitch requirements, and reliability profiles.

waferBumpingUbm.ubm1Title

waferBumpingUbm.ubm1Desc

waferBumpingUbm.ubm2Title

waferBumpingUbm.ubm2Desc

waferBumpingUbm.ubm3Title

waferBumpingUbm.ubm3Desc

waferBumpingUbm.ubm4Title

waferBumpingUbm.ubm4Desc

waferBumpingUbm.ubm5Title

waferBumpingUbm.ubm5Desc

waferBumpingUbm.ubm6Title

waferBumpingUbm.ubm6Desc

Bonding Process Flow

01

Tl 1Title

Tl 1Desc

02

Tl 2Title

Tl 2Desc

03

Tl 3Title

Tl 3Desc

04

Tl 4Title

Tl 4Desc

05

Tl 5Title

Tl 5Desc

Typical Applications

Flip-Chip for High-Performance ICs

Cu pillar and solder bump flip-chip interconnects for CPUs, GPUs, FPGAs, and high-speed SerDes. Low inductance (< 0.1nH) and resistance path. Improved power delivery and signal integrity vs wire bond.

3D-IC Memory Stacking (HBM)

Ultra-fine-pitch (10–40μm) Cu/SnAg micro-bumps for HBM die-to-die and die-to-wafer stacking. Through-silicon via (TSV) compatible. Ultra-thin die handling (< 50μm). Thermocompression bonding at < 280°C.

CIS & Optical Sensor Assembly

Fine-pitch solder bumps and Cu pillars for CMOS image sensor (CIS) flip-chip assembly. Low-temperature bonding for backside-illuminated (BSI) sensors. High interconnect density for large-format sensors.

RF & mmWave Devices

Au stud bumps and Cu pillars for RFIC, mmWave PA/LNA, and antenna-in-package. Low parasitic inductance for > 20GHz applications. Au-Au thermocompression bonding for lowest loss. GaAs and GaN-on-SiC compatible.

LED & Optoelectronic Assembly

Au stud bumps for LED flip-chip and micro-LED display assembly. High thermal conductivity for heat dissipation. Fine-pitch capability for high-resolution displays. GaN-on-sapphire and GaAs compatible.

Reliability Testing

Environmental reliability testing includes temperature cycling, HAST, high-temperature storage, and mechanical shock per MIL-STD and JEDEC standards. Bonded wafer pairs are qualified for your application-specific environmental conditions.

Quality Assurance

Our metrology laboratory maintains ISO 17025 accreditation with NIST-traceable reference standards. All measurement equipment undergoes daily calibration verification with certified reference wafers, and our measurement uncertainty is documented for each parameter type.

Need Wafer Bumping Services?

Specify your bump type, pitch, UBM requirements, and wafer specifications — our team will respond with a detailed quotation within 24 hours.

ISO 9001 Certified JEDEC Reliability Meta Aoi RoHS Compliant