台積電CoPoS — 310×310mm方形矽晶圓
第一代台積電CoPoS 310mm×310mm方形矽面板，用於面板級先進封裝。以玻璃核心三明治結構取代CoWoS圓形中介層，較Ø300mm晶圓增加36%可用面積。NVIDIA Rubin GPU + HBM4，13–15 TB/s頻寬。商業化目標：2028年。
TSMC CoPoS — The Round-to-Square Revolution
In June 2026, TSMC formally locked in 310mm × 310mm as the first-generation standard for its CoPoS (Chip-on-Panel-on-Substrate) advanced packaging platform — the panel-level successor to CoWoS. This decision marks the semiconductor industry’s definitive pivot from round silicon wafers to square panel substrates, a shift as consequential as the transition from 200mm to 300mm wafers two decades ago.
CoPoS replaces CoWoS’s round silicon interposer with a square panel that delivers ~36% more usable area (96,100 mm² vs. ~70,700 mm² for Ø300mm), eliminates chord-cut perimeter waste inherent to circular substrates, and enables rectangular die layouts impossible on round wafers. The 310mm dimension was deliberately chosen as the maximum size compatible with existing 300mm equipment, requiring only minor adjustments — a strategic compromise that avoids the multi-billion-dollar retooling costs of a wholesale form-factor change [$TRAE_REF](https://www.eet-china.com/mp/a504760.html).
TSMC has confirmed that NVIDIA will be the launch customer for CoPoS. A single 310×310mm panel accommodates 4 NVIDIA Rubin-class GPU dies plus HBM4/HBM4E stacks, delivering a theoretical peak memory bandwidth of 13–15 TB/s — approximately 3× the throughput of current CoWoS-L packages [$TRAE_REF](https://www.eet-china.com/mp/a504760.html).
Why 310×310mm? The Equipment Compatibility Sweet Spot
TSMC evaluated multiple panel dimensions — 310×310mm, 510×515mm, and 600×600mm — before standardizing on the smallest. The rationale is pragmatic: every existing 300mm wafer tool (lithography steppers, CMP polishers, PVD/CVD chambers, metrology stations) can be adapted to 310×310mm panels with software reconfiguration and minor chuck modifications. Larger formats would require entirely new equipment ecosystems with decade-long qualification cycles [$TRAE_REF](https://www.trendforce.com/news/2026/05/19/news-equipment-maker-schmid-flags-tsmc-panel-level-packaging-push-310x310mm-progress-glass-integration-under-review/).
310×310
TSMC CoPoS Gen 1 — 300mm tool compatible. 4 NVIDIA GPUs + HBM4. Target: 2028 production. Maximum ROI with minimum retooling.
510×515
TSMC CoPoS Gen 2 — New tooling required. 9 reticles, 36 HBM4E stacks, ~30 TB/s. Target: 2028 demo → post-2030 production.
600×600
Industry horizon — Samsung, Intel, SCHMID exploring. Glass-core-first approach. Target: post-2030 for ultra-scale AI training clusters.
CoPoS Architecture — Three-Layer Sandwich with Glass Core
TSMC’s CoPoS uses a three-layer sandwich structure fundamentally different from the organic substrate + silicon interposer stack in CoWoS. The defining innovation is replacing the silicon interposer with a high-flatness glass core featuring Through-Glass Vias (TGV) for vertical interconnects and thermal management [$TRAE_REF](https://www.eet-china.com/mp/a504760.html).
Ajinomoto Build-up Film resin layer. Chips (GPU, HBM stacks) are flip-chip bonded directly onto this surface via microbumps. Provides mechanical compliance and electrical isolation.
Multi-layer Cu damascene interconnects fanning out chip I/Os across the full 310×310mm panel area. Line/space down to 1/1μm (future: 0.5/0.5μm).
High-flatness glass substrate (400–800μm) with Through-Glass Vias (TGV) for vertical interconnects. Near-zero CTE mismatch with silicon. Superior thermal conductivity vs. organic substrates. Replaces traditional silicon interposer.
Symmetrical ABF build-up on reverse side for warpage balance. Provides second-level interconnect to the system board (BGA/LGA pad array).
Technical Specifications — 310×310mm Square Substrate
| Parameter | Specification |
|---|---|
| Format | 310mm × 310mm square panel (first-generation CoPoS standard) |
| Material | Single-crystal silicon (monocrystalline), CZ-grown 18″-equivalent ingot |
| Diagonal | ~438mm (≈ 17.2″); requires 18″ crystal pulling capability |
| Thickness | Substrate dependent: Si interposer 100–200μm; glass core 400–800μm |
| Surface Finish | CMP-polished (SSP/DSP); Ra < 0.5nm RMS — epi-ready optional |
| TTV | ≤ 2μm across full 310mm square (tight spec for panel-level lithography) |
| Bow / Warp | ≤ 75μm total after Si₃N₄ stress compensation (TSMC low-gradient bonding process) |
| CMP Uniformity | ±3% within-panel via 128-zone dynamic pressure control (TSMC proprietary) |
| Edge Finish | Ground & chamfered 4-edge profile; compatible with panel-handling EFEM |
| Crystal Orientation | 〈100〉 standard; 〈111〉 on request; off-cut ±0.5° available |
| Dopant Type | P-type (Boron) / N-type (Phosphorus, Arsenic) / Intrinsic (FZ) |
| Resistivity | 0.001 – 10,000 Ω·cm (application-dependent) |
| Packaging | Class 100 cleanroom vacuum-sealed cassette or single-panel shippers |
| Compliance | SEMI M1–M13, ISO 9001:2015, RoHS, REACH |
Key Technical Challenges & TSMC’s Solutions
CMP Uniformity Across 310mm Panel
CriticalProblem: Scaling from Ø300mm round to 310×310mm square causes slurry flow uniformity to degrade from ±2% to ±15%, producing Cu interconnect thickness variation >50nm.
TSMC Solution: Multi-zone dynamic pressure control system with 128 independent pressure actuators that compensate for substrate topography in real time. Achieves ±3% within-panel CMP uniformity — approaching round-wafer levels [$TRAE_REF](https://www.eet-china.com/mp/a504760.html).
Warpage During Thermal Compression Bonding
CriticalProblem: Differential thermal expansion between 310mm glass core and silicon interposer generates up to 500μm bow during standard 15°C/min thermocompression bonding.
TSMC Solution: Low-temperature gradient bonding — ramp rate reduced to 5°C/min with an additional Si₃N₄ stress compensation layer. Total warp compressed to ≤75μm. Yield improved from 32% (2024) to 68% (2026) [$TRAE_REF](https://www.eet-china.com/mp/a504760.html).
From Ingot to 310×310 Panel — Wafering Process
Supply Chain — Square Wafer Suppliers for CoPoS
As of mid-2026, three major silicon wafer manufacturers have publicly confirmed 310×310mm square substrate deliveries to TSMC for CoPoS qualification [$TRAE_REF](https://www.eet-china.com/mp/a504760.html):
GlobalWafers (环球晶圆)
Hsinchu, Taiwan
World’s third-largest silicon wafer manufacturer. Confirmed 310×310mm square monocrystalline silicon wafers in small-volume qualification (May 2026 shareholder meeting). Building cleanroom for Q4 2026 mass production ramp. Chairwoman Doris Hsu noted: “First-phase capacity ~thousands of wafers/month; reserved cleanroom space for modular expansion when demand materializes.”
Tier-1 SupplierShanghai ChaoSilicon (上海超硅)
Shanghai, China
Announced volume delivery of square silicon wafers to a major customer in May 2026 for AI HPC chip CoPoS packaging. The first Chinese silicon supplier to publicly confirm square wafer capability. Manufacturing at its 300mm-capable Shanghai fab.
Qualified SupplierHejing Technology (合晶科技)
Taoyuan, Taiwan
Confirmed completed square wafer sampling to the leading foundry customer with “smooth customer-side progress” (United Daily News, June 2026). Long-standing epitaxial wafer supplier to TSMC with existing process compatibility.
Qualified SupplierTimeline — TSMC CoPoS Roadmap
Supply 310×310mm Square Silicon Wafers for CoPoS?
GINECHIP is actively qualifying 310×310mm square monocrystalline silicon substrates for TSMC CoPoS panel-level packaging supply chains. Contact our substrate engineering team with your specification requirements — side length, thickness, TTV, surface finish, and volume — for a detailed quotation and sampling timeline.