Silicon Interposer
Silicon interposers with TSV and multi-layer RDL for CoWoS, HBM, chiplet integration, and AI/ML accelerator packaging. Available in passive, active, and high-resistivity RF grades up to 300mm.
Overview
The silicon interposer is the critical interconnect fabric at the heart of 2.5D and 3D advanced packaging. It serves as a high-density routing substrate that sits between the chip dies and the organic package substrate, providing the fine-pitch interconnects (L/S down to 0.4/0.4μm) that are impossible to achieve on organic substrates. Through-Silicon Vias (TSVs) provide vertical electrical feedthrough, while multi-layer Cu RDL provides lateral routing between chiplets, HBM stacks, and I/O interfaces.
GINECHIP supplies silicon interposer substrates in passive, active (CoWoS-L with embedded LSI), and high-resistivity RF grades, with TSV aspect ratios up to 15:1 and RDL line/space down to 0.4/0.4μm. Our interposers are available in 200mm and 300mm diameters, with thickness options from 100μm to 775μm. All interposers undergo comprehensive electrical and mechanical metrology including TSV resistance/yield, RDL continuity, void detection, and bump integrity testing.
Interposer Types
Passive TSV Interposer
Most CommonSilicon interposer with TSVs for vertical electrical feedthrough and multi-layer RDL on frontside and/or backside for lateral routing. No active devices — purely a passive interconnect substrate. Used in CoWoS-S, chiplet-based processors, and HBM integration. Offers the highest interconnect density (L/S down to 0.4/0.4μm) and the lowest signal latency of all interposer types.
Active Interposer (CoWoS-L)
Embedded LSISilicon interposer with embedded local silicon interconnect (LSI) dies for active signal buffering, protocol bridging, and power management. The LSI chips are embedded within the interposer dielectric, providing active routing between chiplets without the latency penalty of going off-interposer. CoWoS-L represents the state-of-the-art for AI/ML accelerator integration.
High-Resistivity RF Interposer
RF/mmWaveSilicon interposer fabricated on high-resistivity (> 1,000 Ω·cm) silicon to minimize substrate losses at RF and mmWave frequencies. Enables integration of antenna arrays, beamforming ICs, and transceivers on a single interposer with integrated passive devices (IPDs) for impedance matching and filtering. Used in 5G AiP modules and phased-array radar.
Technical Specifications
| Parameter | Specification |
|---|---|
| Material | Single-crystal silicon (CZ, FZ), High-resistivity Si (> 1,000 Ω·cm for RF) |
| Diameter | 200mm (8″), 300mm (12″) |
| Thickness | 100μm – 775μm (standard), 50μm – 100μm (ultra-thin with temporary carrier) |
| TSV Diameter | 5μm – 100μm (application-dependent) |
| TSV Depth | 20μm – 300μm |
| TSV Aspect Ratio | Up to 15:1 (via-first), up to 10:1 (via-middle) |
| RDL L/S | 0.4/0.4μm (fine-pitch), 2/2μm (standard), 5/5μm (coarse) |
| RDL Layers | 1 – 8 metal layers (Cu damascene or semi-additive) |
| Dielectric | SiO₂ (CVD), Si₃N₄, low-k polymer (BCB, PI) |
| Bump Type | μ-bump (Cu pillar + SnAg cap), C4 bump (SAC305/SnPb), Cu hybrid bond pad |
| Bump Pitch | 10μm (hybrid bond) – 400μm (C4) |
| Interposer Footprint | Up to 2.5× reticle size (~2,100mm²) with stitching |
| TTV | ≤ 2μm (200mm), ≤ 3μm (300mm) |
| Bow / Warp | ≤ 30μm Bow, ≤ 40μm Warp (300mm, post-TSV) |
| Packaging | Class 100 cleanroom vacuum-sealed cassette or single-wafer shipper |
Applications
TSMC's CoWoS platform is the most widely deployed silicon interposer technology, with production volumes exceeding 2.68 million wafers. The silicon interposer provides the high-density interconnect fabric between logic compute dies, HBM stacks, and I/O chiplets. GINECHIP supplies the starting silicon substrates, TSV-processed wafers, and RDL-metallized interposers for CoWoS production.
HBM stacks (HBM2E, HBM3, HBM3E) require silicon interposers with 1,024-bit wide interfaces and bump pitches of 55μm (μ-bump) to 10μm (hybrid bond). The interposer routes the wide memory bus from the logic die at the base of the HBM stack to the compute die, enabling bandwidths of 1.6 TB/s per stack.
UCIe (Universal Chiplet Interconnect Express) and BoW (Bridge of Wires) standardized interfaces enable heterogeneous chiplet integration on silicon interposers. The interposer provides the physical layer interconnect fabric, supporting UCIe-standard and advanced UCIe-standard data rates of 16–64 GT/s per lane across multiple reticle-sized chiplets.
Large language model (LLM) training and inference accelerators demand interposers with reticle-stitching to accommodate die sizes exceeding 2.5× the reticle limit. The interposer connects multiple compute tiles, HBM stacks, and high-speed SerDes chiplets with bandwidth exceeding 10 TB/s across the interposer.
Data center switch ASICs (51.2T, 102.4T) require interposers for integrating the large switch die with multiple HBM stacks and high-speed SerDes. The interposer's dense routing capability (L/S 0.4/0.4μm) is essential for routing the massive I/O count (2,000+ signal pins) from the switch ASIC to the package substrate.
Multi-die FPGAs and hardware emulation platforms utilize silicon interposers to connect multiple FPGA fabric dies across a single interposer. The interposer provides the high-bandwidth, low-latency die-to-die interconnect fabric that enables the multi-die FPGA to appear as a single logical device.
Quality & Metrology
TSV Resistance & Yield
4-point Kelvin probe measurement on test structures. TSV resistance < 50 mΩ (typical, 10×100μm via). Daisy-chain continuity yield > 99.9% on 1,000-via chains.
TSV Isolation & Leakage
I-V measurement between TSV and silicon substrate. Leakage current < 1 nA at 5V bias. Breakdown voltage > 50V for 200nm thermal SiO₂ liner.
RDL Electrical Test
Continuity and isolation testing on RDL test structures. Line resistance conforms to target sheet resistance (Cu: 1.7 μΩ·cm bulk). Inter-layer dielectric breakdown > 5 MV/cm.
X-Ray / Acoustic Microscopy
Void detection in TSV Cu fill and bump interconnects. Zero voids > 1μm in TSV fill. C-SAM for interfacial delamination inspection post-reflow.
TTV / Bow / Warp Interferometry
Full-wafer topography post-TSV and post-RDL. TTV ≤ 2μm, Bow ≤ 30μm, Warp ≤ 40μm for 300mm wafers. Critical for subsequent bonding and assembly steps.
AFM Surface Roughness
Post-CMP surface roughness measurement. Cu dishing < 50nm, dielectric erosion < 30nm. Post-CMP Ra < 1nm for hybrid bonding compatibility.
FIB-SEM Cross-Section
Focused ion beam milling and SEM imaging of TSV and RDL cross-sections. Verification of barrier/seed continuity, Cu fill quality, and interface integrity.
Bump Shear / Pull Testing
Mechanical integrity testing of μ-bumps and C4 bumps per JEDEC JESD22-B117. Shear strength > 50 MPa for Cu pillar bumps. Pull strength > 5g for C4 bumps.
Request Silicon Interposer Quote
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