TGV Wafer — Through-Glass Via
Through-Glass Via (TGV) wafers with laser-drilled and metallized vias for 2.5D glass interposers, mmWave AiP, CoPoS integration, and photonic interposers. Borofloat 33, fused silica, and alkali-free grades.
Overview
Through-Glass Via (TGV) technology is the glass-substrate analog of Through-Silicon Via (TSV), enabling vertical electrical interconnects through glass wafers for 2.5D and 3D packaging. Unlike silicon, glass is an electrical insulator (resistivity > 10¹⁰ Ω·cm), eliminating the need for a dielectric isolation liner that is mandatory in TSV fabrication. The low dielectric constant (εr = 4.0–5.5) and low loss tangent (tan δ < 0.005) of glass also reduce signal attenuation, making TGV interposers superior to silicon interposers for RF and mmWave applications.
GINECHIP supplies TGV wafers in Borofloat 33, fused silica quartz, and alkali-free glass grades, with via diameters from 10μm to 200μm and aspect ratios up to 10:1. Our TGV formation methods include laser-induced deep etching (LIDE), focused electrical discharge, and ultrashort pulse laser ablation. All TGVs are metallized with PVD barrier/seed layers followed by Cu electroplating, with optional Ni/Au surface finish. Comprehensive metrology — including SEM cross-section, 4-point Kelvin resistance, and X-ray void detection — is performed on every lot.
TGV Formation Methods
Laser-Induced Deep Etching (LIDE)
High ARLIDE uses a two-step process: femtosecond laser modification of the glass to create a modified track, followed by wet chemical etching that preferentially removes the laser-modified material. This produces smooth-walled, high-aspect-ratio (up to 10:1) TGVs with minimal micro-cracking and residual stress. The LIDE process is compatible with borosilicate, fused silica, and alkali-free glass substrates from 100mm to 300mm diameter.
Focused Electrical Discharge
High SpeedFocused electrical discharge (also known as electrical discharge machining or spark-assisted chemical engraving) uses a high-voltage discharge between a tool electrode and the glass surface to locally ablate material. This method offers the highest throughput (up to 1,000 vias/second) for via diameters of 50–200μm. Best suited for coarse-pitch TGV interposers where throughput is prioritized over minimum feature size.
Ultrashort Pulse Laser Ablation
VersatileDirect femtosecond or picosecond laser ablation of glass without subsequent wet etching. The ultrashort pulse duration (< 1 ps) minimizes heat-affected zone and micro-cracking. This method offers the greatest flexibility in via geometry — tapered, straight, or shaped sidewalls — and is compatible with all glass types. Throughput is lower than LIDE or discharge methods but is suitable for prototyping and low-volume production.
Technical Specifications
| Parameter | Specification |
|---|---|
| Substrate Material | Borofloat 33, Fused silica quartz, AN100 alkali-free glass, Sapphire Al₂O₃ |
| Diameter | 100mm (4″), 150mm (6″), 200mm (8″), 300mm (12″) |
| TGV Formation Method | Laser-induced deep etching (LIDE), Focused electrical discharge, Wet HF etching, Ultrashort pulse laser ablation |
| Via Diameter | 10μm – 200μm (application-dependent) |
| Via Depth | 100μm – 1,100μm (through-wafer) |
| Aspect Ratio | Up to 6:1 (laser), up to 10:1 (LIDE), up to 3:1 (wet etch) |
| Via Pitch | 50μm – 500μm (minimum pitch depends on diameter) |
| Via Density | Up to 10⁴ vias/mm² (10μm diameter, 50μm pitch) |
| Sidewall Angle | 88° ± 1° (laser), 89° ± 0.5° (LIDE) |
| Sidewall Roughness | < 200nm Ra (laser), < 100nm Ra (LIDE), < 50nm (wet etch + anneal) |
| Metallization | Cu (PVD seed + electroplating), Ti/Cu, TiW/Cu, Cr/Au, Cu/Ni/Au |
| Isolation Liner | PECVD SiO₂ (100–500nm), ALD Al₂O₃ (50–100nm), polymer (BCB, SU-8) |
| Metallization Conformality | > 50% step coverage (PVD), > 90% (ALD barrier + CVD seed) |
| Via Resistance | < 100 mΩ (typical, 50×500μm via, solid Cu fill) |
| Packaging | Interleaved cleanroom paper, vacuum-sealed single-wafer cassette |
Applications
TGV wafers are the core building block of glass interposers for 2.5D packaging. The low dielectric constant (εr = 4.0–5.5) and low loss tangent (tan δ < 0.005) of glass reduce signal attenuation compared to silicon interposers, making them ideal for high-speed digital and RF applications. Multi-layer RDL on both sides of the TGV wafer provides the lateral routing fabric between chiplets, HBM stacks, and package substrates.
The low dielectric loss of glass substrates combined with TGV interconnects enables low-loss RF transitions from antenna to beamforming IC. TGV-based interposers for 5G mmWave (28/39 GHz) and 6G (100+ GHz) antenna-in-package modules achieve insertion loss < 0.5 dB per transition, significantly better than organic substrate-based alternatives.
CoPoS (Chip-on-Panel-on-Substrate) architecture relies on TGV-metallized glass panels as the interposer substrate. The TGVs provide vertical interconnect between the frontside RDL (chip-to-chip routing) and the backside package substrate interface. Panel-level TGV formation on 510×515mm glass panels enables the 4.5× throughput advantage of CoPoS over wafer-level approaches.
TGV wafers with integrated optical waveguides (written by femtosecond laser in fused silica) enable co-integration of electrical interconnects (Cu-filled TGVs) and optical interconnects (waveguides) on a single glass substrate. This is critical for co-packaged optics (CPO) where both electrical and optical signals must be routed between the photonic engine and the switch ASIC.
TGV wafers provide hermetic, low-parasitic electrical feedthroughs for MEMS wafer-level packaging. The electrical insulation of glass (resistivity > 10¹⁰ Ω·cm) eliminates the need for dielectric isolation layers required on silicon TSV wafers, simplifying the fabrication process and reducing parasitic feedthrough capacitance for capacitive MEMS sensors.
Through-glass vias in borosilicate or fused silica wafers enable fluidic interconnects between microfluidic layers in lab-on-chip and organ-on-chip devices. The optical transparency of glass allows real-time fluorescence microscopy of the fluidic channels, while the chemical inertness ensures compatibility with biological samples and aggressive reagents.
Quality & Metrology
Via Geometry SEM/FIB
SEM cross-section and FIB milling for via diameter, depth, sidewall angle, and sidewall roughness measurement. 100% automated optical inspection (AOI) for via placement accuracy (±2μm) and via diameter uniformity (±5%).
Via Resistance (4-Point Kelvin)
4-point Kelvin probe measurement on individual TGVs and daisy-chain test structures. TGV resistance < 100 mΩ (typical, 50×500μm Cu-filled via). Daisy-chain continuity yield > 99% on 1,000-via chains.
Isolation / Leakage Current
I-V measurement between adjacent TGVs and between TGV and substrate surface. Leakage current < 1 nA at 5V bias for 200nm PECVD SiO₂ liner. Isolation resistance > 10¹⁰ Ω between adjacent vias.
X-Ray / CT Inspection
X-ray microscopy and computed tomography for void detection in Cu-filled TGVs. Zero voids > 5μm in fill. Full-wafer X-ray inspection available for production lots.
AFM Surface Roughness
Post-CMP surface roughness measurement. Cu dishing < 50nm, glass erosion < 30nm. Post-CMP Ra < 1nm for RDL lithography compatibility.
TTV / Bow / Warp Interferometry
Full-wafer topography post-TGV formation and post-CMP. TTV ≤ 5μm, Bow ≤ 25μm for 200mm glass wafers. Critical for subsequent RDL lithography depth-of-focus requirements.
Cross-Sectional SEM (EDS)
Energy-dispersive X-ray spectroscopy (EDS) on TGV cross-sections for barrier/seed continuity verification, Cu fill quality, and intermetallic formation detection at the Cu/barrier interface.
Thermal Cycling Reliability
Temperature cycling (-55°C to +150°C, 1,000 cycles) per JEDEC JESD22-A104. TGV resistance change < 10% post-cycling. No delamination at Cu/glass, Cu/liner, or liner/glass interfaces per C-SAM inspection.
Request TGV Wafer Quote
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