CMP Bonding Wafer
CMP-polished silicon wafers with sub-0.2nm RMS surface roughness for hybrid bonding, fusion bonding, and DBI. Cu/SiO₂, SiO₂/SiO₂, and direct bond interconnect grades for 3D IC, HBM4, and CIS stacking.
Overview
CMP (Chemical Mechanical Polishing) bonding wafers are the foundational substrate for hybrid bonding, fusion bonding, and direct bond interconnect (DBI) technologies — the critical enablers of 3D IC stacking, HBM4 memory, and advanced CMOS image sensors. These wafers undergo precision CMP to achieve surface roughness below 0.2nm RMS, Cu pad recess control within 1–5nm, and total thickness variation under 1μm — specifications that are essential for achieving void-free, high-yield wafer-to-wafer bonding.
GINECHIP supplies CMP bonding wafers in Cu/SiO₂ hybrid bonding, SiO₂/SiO₂ fusion bonding, and DBI-compatible grades. Our wafers are available in diameters from 100mm to 300mm, with CMP processes tailored to your specific pad layout, pattern density, and bonding requirements. Every wafer undergoes comprehensive metrology including AFM surface roughness, Cu dishing profilometry, TXRF metal contamination analysis, and surface energy measurement.
Bonding Types
Cu/SiO₂ Hybrid Bonding
Highest DensityCMP-polished wafers with recessed Cu pads (1–5nm recess) in a SiO₂ dielectric matrix. During hybrid bonding at room temperature, the SiO₂ surfaces bond first via van der Waals forces, then the Cu pads expand during annealing (200–400°C) to form a hermetic, conductive bond. This enables interconnect pitches down to 1μm — the highest density of any bonding technology. Critical for 3D IC stacking, backside illuminated CMOS image sensors, and HBM3E/HBM4 memory stacks.
Fusion Bonding (SiO₂/SiO₂)
Hermetic SealUltra-smooth (< 0.2nm RMS) SiO₂ surfaces bonded at room temperature with subsequent anneal (300–1,100°C) to form a covalent Si-O-Si bond. No intermediate layer — the bond interface is indistinguishable from bulk SiO₂. Provides hermetic sealing and near-zero thermal resistance. Used for SOI wafer fabrication, MEMS wafer-level packaging, and silicon photonics integration.
Direct Bond Interconnect (DBI)
Hybrid BondA proprietary hybrid bonding technology (DBI by Adeia/Xperi) where CMP-planarized Cu and dielectric surfaces are bonded at room temperature, then annealed. The key differentiator is the recessed Cu pad design that prevents Cu oxidation and enables high-yield, void-free bonding across full wafers. DBI is the de facto standard for 3D-stacked CMOS image sensors and emerging HBM4 memory stacks.
Technical Specifications
| Parameter | Specification |
|---|---|
| Material | Single-crystal silicon (CZ, FZ), SOI, thermal oxide, nitride-coated |
| Diameter | 100mm (4″), 150mm (6″), 200mm (8″), 300mm (12″) |
| Thickness | 200μm – 775μm (standard), 50μm – 100μm (ultra-thin) |
| Surface Roughness (AFM RMS) | < 0.2nm (1×1μm scan), < 0.15nm (advanced CMP) |
| TTV (Post-CMP) | ≤ 1μm (200mm), ≤ 2μm (300mm) |
| Cu Dishing | < 30nm (standard), < 15nm (advanced) |
| Dielectric Erosion | < 25nm (standard), < 10nm (advanced) |
| Bow / Warp | ≤ 20μm Bow, ≤ 25μm Warp (200mm post-CMP) |
| Particles @ 0.2μm | ≤ 10 particles (post-CMP clean) |
| Surface Energy | > 45 mN/m (hydrophilic activation), > 30 mN/m (hydrophobic) |
| Metal Contamination | Fe, Cu, Ni, Cr < 5×10¹⁰ atoms/cm² (TXRF) |
| CMP Process | Cu CMP, oxide CMP, W CMP, Si CMP, STI CMP, ILD CMP |
| Post-CMP Clean | Brush scrub, megasonic, cryogenic aerosol, or chemical clean |
| Edge Exclusion | 2mm (standard), 1mm (advanced), edge-bead removal available |
| Packaging | Class 10 cleanroom vacuum-sealed single-wafer shipper with purge gas |
Applications
Hybrid bonding with CMP-polished Cu/SiO₂ wafers enables face-to-face and face-to-back 3D stacking of logic-on-logic, memory-on-logic, and sensor-on-logic. The sub-1μm interconnect pitch achievable with hybrid bonding is 1,000× denser than μ-bump interconnects, enabling unprecedented bandwidth density (> 10 TB/s/mm²) between stacked dies.
Next-generation HBM4 memory stacks transition from μ-bump to hybrid bonding interconnects, reducing the bump pitch from 55μm to < 10μm. CMP bonding wafers with sub-0.2nm RMS surface roughness and controlled Cu recess are essential for achieving the > 99.9% interconnect yield required for 16-Hi HBM4 stacks.
Hybrid bonding enables the separation of the photodiode layer and the readout circuit layer in stacked CMOS image sensors. The CMP-bonded wafer pair provides the thousands of pixel-level interconnects between the two layers, with the bond interface being optically transparent and electrically conductive. This is the dominant CIS architecture for smartphone cameras.
Fusion bonding of a CMP-polished silicon wafer to an oxidized handle wafer, followed by the Smart Cut process (ion implantation + thermal splitting), produces SOI wafers with device-layer thickness from 50nm to 1.5μm. The CMP surface quality of both the donor and handle wafers directly determines the SOI buried oxide interface quality.
Heterogeneous integration of III-V materials (InP, GaAs) onto silicon photonic circuits via direct bonding requires CMP-planarized surfaces with sub-nanometer roughness. The bonded interface must be optically transparent and mechanically robust for laser integration, modulator fabrication, and photodetector coupling.
Fusion and anodic bonding of CMP-polished cap wafers to MEMS device wafers provides hermetic, vacuum-tight encapsulation for inertial sensors, pressure sensors, and RF MEMS switches. The CMP surface finish ensures void-free bonding across the entire wafer, critical for long-term reliability of hermetically sealed MEMS devices.
Quality & Metrology
AFM Surface Roughness
Atomic force microscopy over 1×1μm, 10×10μm, and 50×50μm scan areas. Surface roughness Ra < 0.2nm (1×1μm) for fusion bonding, Ra < 0.15nm (1×1μm) for advanced hybrid bonding. Cu pad recess (1–5nm) verified by AFM line scan across pad/dielectric boundary.
Cu Dishing & Erosion Profilometry
Stylus or optical profilometry across Cu pad arrays of varying pattern density (10%–90%). Cu dishing < 30nm, dielectric erosion < 25nm. Pattern-dependent dishing maps provided for bond yield prediction.
TXRF Metal Contamination
Total reflection X-ray fluorescence spectroscopy for surface metal contamination. Fe, Cu, Ni, Cr < 5×10¹⁰ atoms/cm². Critical for preventing metal-induced junction leakage and gate oxide integrity degradation.
Contact Angle / Surface Energy
Sessile drop contact angle goniometry with DI water and diiodomethane. Surface energy > 45 mN/m post-hydrophilic activation. Ensures consistent bond initiation and propagation across the wafer.
Laser Surface Particle Scan
Particle inspection at 0.2μm sensitivity per SEMI M53. Standard specification: ≤ 10 particles. Tighter specs (≤ 5 @ 0.16μm) for hybrid bonding where a single particle can cause a millimeter-scale void.
TTV / Bow / Warp Interferometry
Full-wafer topography post-CMP. TTV ≤ 1μm (200mm), Bow ≤ 20μm. Critical for achieving uniform bond wave propagation and avoiding edge-non-bonded regions.
X-Ray Photoelectron Spectroscopy (XPS)
Surface chemical analysis for CMP residue detection (slurry particles, organic inhibitors, corrosion inhibitors). Confirms surface cleanliness and chemical state (e.g., Cu oxidation state) before bonding.
C-SAM Bond Interface Inspection
C-mode scanning acoustic microscopy for post-bond void detection. Resolution < 5μm void detection. Full-wafer void maps provided for bond quality assessment. > 99.9% bond area coverage specification.
Request CMP Bonding Wafer Quote
Specify your bonding type, pad layout, and surface specifications for a tailored quotation.