Through-Silicon Via (TSV)

Stat Value 1Stat Label 1

Stat Value 2Stat Label 2

Stat Value 3Stat Label 3

Stat Value 4Stat Label 4

H 2Overview

Overview Paragraph 1

Overview Paragraph 2

H 2Modules

throughSiliconViaTsv.spec1Name

throughSiliconViaTsv.spec1Desc

Vias: 5–100μm diameterDepth: 20–300μmAspect ratio: up to 15:1Sidewall angle: 89° ± 0.5°Scallop control: < 50nmCryogenic smooth etch option

throughSiliconViaTsv.spec2Name

throughSiliconViaTsv.spec2Desc

Thermal SiO₂: 100nm–2μmPECVD SiO₂/Si₃N₄: 50–500nmConformality: > 90% (thermal), > 70% (PECVD)Breakdown: > 8 MV/cm (thermal)Process temp: 900–1100°C (thermal), 250–400°C (PECVD)Capacitance: 50–200 pF/via (design dependent)

throughSiliconViaTsv.spec3Name

throughSiliconViaTsv.spec3Desc

Barrier: Ta (PVD), TaN (PVD/ALD)Seed: Cu (PVD), 100–500nmBarrier thickness: 5–50nmStep coverage: > 25% (bottom, PVD)ALD barrier: > 95% conformalityAdhesion: no delamination after anneal

throughSiliconViaTsv.spec4Name

throughSiliconViaTsv.spec4Desc

Cu thickness: 3–25μm overfieldFill type: bottom-up superfillingChemistry: CuSO₄/H₂SO₄ + additivesPlating rate: 0.3–1.0 μm/minPost-plate anneal: 200–400°C, N₂X-ray inspection for void detection

throughSiliconViaTsv.spec5Name

throughSiliconViaTsv.spec5Desc

Cu removal rate: 300–600 nm/minCu dishing: < 50nmDielectric erosion: < 30nmPost-CMP Ra: < 1nm (AFM)Clean: particles < 20 adds @ 0.2μmNi/Au finish: 3–5μm Ni, 0.05–0.2μm Au

H 2Flow Opts

throughSiliconViaTsv.flow1Name

throughSiliconViaTsv.flow1Desc

TSV after FEOL, before BEOLVia diameter: 5–20μmThermal budget: compatible with BEOLAdvantage: dense TSV arraysChallenge: Cu protrusion during BEOL thermal cycles

throughSiliconViaTsv.flow2Name

throughSiliconViaTsv.flow2Desc

TSV after BEOL, from backsideVia diameter: 20–100μmThermal budget: < 400°C maxAdvantage: no FEOL/BEOL disruptionChallenge: alignment to buried pads

H 2Process Flow

throughSiliconViaTsv.flowStep1Title

throughSiliconViaTsv.flowStep1Desc

throughSiliconViaTsv.flowStep2Title

throughSiliconViaTsv.flowStep2Desc

throughSiliconViaTsv.flowStep3Title

throughSiliconViaTsv.flowStep3Desc

throughSiliconViaTsv.flowStep4Title

throughSiliconViaTsv.flowStep4Desc

throughSiliconViaTsv.flowStep5Title

throughSiliconViaTsv.flowStep5Desc

throughSiliconViaTsv.flowStep6Title

throughSiliconViaTsv.flowStep6Desc

H 2Quality

Col Param	Col Target	Col Method
throughSiliconViaTsv.qm1Param	< 50 mΩ (typical, 10×100μm via)	4-point Kelvin probe on test structures
throughSiliconViaTsv.qm2Param	> 99.9% (1,000-via chain)	4-point resistance continuity
throughSiliconViaTsv.qm3Param	> 50V (for 200nm thermal SiO₂)	Ramped voltage I-V sweep
throughSiliconViaTsv.qm4Param	< 1 nA at 5V (silicon-to-TSV)	I-V measurement, Si grounded, TSV biased
throughSiliconViaTsv.qm5Param	< 100nm @ 400°C anneal	AFM / profilometry
throughSiliconViaTsv.qm6Param	Zero voids > 1μm in fill	X-ray microscopy / acoustic microscopy
throughSiliconViaTsv.qm7Param	< 50nm (Bosch process)	SEM cross-section
throughSiliconViaTsv.qm8Param	50–200 pF (dependent on geometry)	C-V measurement at 1 MHz

Quality Note

H 2Via Fill

Via Fill Paragraph 1

Via Fill Paragraph 2

Via Fill Paragraph 3

H 2App Domains

App 1Title

App 1Desc

App 2Title

App 2Desc

App 3Title

App 3Desc

App 4Title

App 4Desc

H 2Barrier

Barrier Paragraph 1

Barrier Paragraph 2

CTA Title

CTA Description

Angebot anfordern Ingenieure kontaktieren

Meta 1 Meta 2 Meta 3 Meta 4