RDL & Bump Wafer — Wafer-Level-Dienste | GINECHIP

0.4–5μm L/SStat Rdl Rules

1–8 LayersStat Stack Height

10–500μmStat Bump Pitch

200mm, 300mmStat Wafer Diam

Übersicht

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Heading Rdl Tiers

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L/S: 5/5μmCu thickness: 5–8μmVia: 20–30μm diaPI dielectric: 5–8μm thickLayers: 1–3Bump pitch: 300–500μm

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L/S: 2/2μmCu thickness: 3–5μmVia: 10–15μm diaBCB or advanced PI dielectricLayers: 2–5Bump pitch: 130–300μm

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L/S: 0.4/0.4μmCu thickness: 1–3μmVia: 5–10μm diaSiO₂ dielectric (CVD)Layers: 2–8Damascene Cu + TaN/Ta barrier

Heading Bump Options

Wafer bumping creates interconnect structures on semiconductor wafers for flip-chip assembly. Our comprehensive bumping platform supports multiple materials, pitches, and aspect ratios across 100mm to 300mm wafers.

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Alloys: SAC305, SAC405, SnPbPitch: 130–400μmHeight: 50–100μmUBM: Ti/Cu or TiW/CuReflow: wafer-level

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Pillar height: 20–80μmSolder cap: 10–25μm SnAgPitch: 40–130μmNi barrier optionAR: 2:1–5:1

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Pitch: 10–55μmDiameter: 5–25μmCu/Ni/SnAg stackHybrid bonding compatibleMass reflow or TCB

Heading Process Flow

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Heading Key Apps

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Heading Ipd

Integrated Passive Devices fabricated in the RDL layers provide capacitors, inductors, and resistors directly on the wafer surface. IPD integration reduces component count, minimizes parasitics, and improves electrical performance for RF and power management applications.

Heading Quality

Our quality management system is certified to ISO 9001:2015 with additional compliance to SEMI standards, RoHS, REACH, and Conflict Minerals regulations. Each shipment includes a certificate of conformance with lot traceability back to the original ingot.

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RDL Bump Wafer