Silizium-Wafersubstrat
Das grundlegende Material für MEMS, CMOS, Leistungsbauelemente und Photonik.
Übersicht
Siliziumwafer bleiben das dominierende Substrat — über 90% des globalen Halbleitersubstratmarktes. GINECHIP beschafft und vertreibt Siliziumsubstrate über alle Güteklassen, Durchmesser und Spezifikationen in über 50 Ländern.
Prime-CZ-Wafer, ultraflache FZ-Wafer, SOI-Substrate oder Test-Wafer — unsere Lieferkette liefert konstante Qualität mit voller Rückverfolgbarkeit.
Silicon Wafer Product Categories
Select a category to explore detailed specifications, manufacturing methods, and request a quotation.
Prime Silicon Wafers
Device-grade CZ & FZ substrates. Sub-nanometer roughness, tight resistivity and thickness tolerances for CMOS, MEMS, and power devices.
Test / Monitor Wafers
Cost-optimized wafers for fab equipment qualification, process monitoring, and daily tool checks. Consistent electrical and mechanical properties.
Dummy / Mechanical Wafers
Lowest-cost non-production wafers for furnace fill, tool setup, thermal uniformity control, and mechanical handling qualification.
Reclaimed Wafers
Chemically-mechanically stripped and repolished wafers restored to near-prime quality. 30–60% cost savings with up to 5 reclaim cycles.
Ultra-Thin / Taiko Wafers
Wafers thinned to 20μm with Taiko ring process for 3D-IC stacking, power devices, BSI sensors, and advanced packaging.
FZ High-Resistivity Wafers
Float Zone silicon with >10 kΩ·cm resistivity and extreme purity. O₂/C < 5×10¹⁵. Preferred substrate for RFICs, photonics, and radiation detectors.
SOI Wafers
Silicon-on-Insulator substrates with device layer on buried oxide. Smart Cut, BESOI, SIMOX, ELTRAN. For RF-SOI, FD-SOI, MEMS, photonics.
Thermal Oxide on Silicon
High-quality thermally-grown SiO₂ layers 10nm–4μm. Dry, wet, and pyrogenic oxidation for gate oxides, diffusion masks, and etch-stop layers.
Nitride on Silicon (Si₃N₄)
LPCVD & PECVD Si₃N₄ films 20nm–2μm. Stoichiometric and low-stress formulations. Diffusion barrier, passivation, MEMS hard mask.
Silicon Epi Wafers
CVD homoepitaxial Si on Si. Custom doping and thickness 0.5–200μm. For CMOS sensors, power MOSFETs, IGBTs, and BiCMOS.
Kristallzuchtverfahren
Wir liefern Substrate aus folgenden Ingot-Zuchtverfahren:
CZ (Czochralski)
Häufigste Methode — Ziehen eines Einkristalls aus Siliziumschmelze. Produziert 200/300-mm-Wafer.
FZ (Float Zone)
Ultrahochreines Silizium durch Zonenschmelzen. Unverzichtbar für IGBTs, HF-Transistoren.
MCZ (Magnetisches CZ)
Magnetfeld während CZ-Wachstum unterdrückt Konvektion. Bevorzugt für CCD/CMOS.
Technische Spezifikationen
| Parameter | Verfügbarer Bereich |
|---|---|
| Diameter | 100mm (4″), 150mm (6″), 200mm (8″), 300mm (12″) |
| Type / Dopant | P-type (Boron), N-type (Phosphorus, Arsenic, Antimony) |
| Resistivity | 0.001–10,000 Ω·cm (custom ranges available) |
| Orientation | 〈100〉, 〈111〉, 〈110〉 (off-cut angles available) |
| Thickness | 200μm–1000μm (standard SEMI specs ± custom) |
| Polish | SSP (Single-Side), DSP (Double-Side), CMP-finished |
| Backside | Bright-etched, Lapped, Polysilicon, Oxide/Nitride layer |
| TTV / Bow / Warp | As low as < 2μm TTV, < 5μm Bow, < 10μm Warp |
| Particles | ≤ 10 particles @ 0.2μm (Class 1 cleanroom packaging) |
Oberflächengüten & Rückseitenbehandlung
Vorderseitenpolitur
- CMP (Chemical-Mechanical Polish) — sub-nanometer RMS roughness for advanced lithography
- SSP (Single-Side Polished) — standard for most MEMS and CMOS processes
- DSP (Double-Side Polished) — required for double-side alignment photolithography
- Epi-Ready — surface prepared for epitaxial growth with < 5Å native oxide
Rückseitenoptionen
- Bright-Etched — acid-etched for uniform appearance
- Lapped — mechanically ground for thickness control
- Polysilicon Backseal — gettering layer for heavy-metal contamination control
- Thermal Oxide / LPCVD Nitride — dielectric backside for etch-stop or isolation
- Custom Backside Film Stacks — oxide-nitride, ONO, or metal backside
Anwendungen
Qualität & Zertifizierung
Jedes Los wird mit Konformitätszertifikat geliefert. ISO 9001:2015.
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