Redistribution Layer (RDL)
Single and multi-layer Cu redistribution layer processing using semi-additive process (SAP) with polymer dielectrics — enabling fine-pitch routing for fan-out wafer-level packaging, 2.5D interposers, and chiplet integration.
Service Overview
Redistribution layers (RDL) are the interconnect backbone of modern advanced packaging — fanning out the dense I/O pitch of an integrated circuit die to the coarser pitch of the package substrate or printed circuit board. In fan-out wafer-level packaging (FOWLP), RDL enables electrical connection from the die pads (typically at 40–100μm pitch) to BGA balls (at 300–500μm pitch), accommodating the fan-out area beyond the die footprint. In 2.5D interposers and chiplet architectures, RDL provides the lateral wiring between multiple dies on a shared substrate.
GINECHIP's RDL service provides complete, production-ready redistribution layer fabrication using the semi-additive process (SAP) with Cu metallization and photosensitive polymer dielectrics (polyimide, BCB, or PBO). We support single-layer and multi-layer RDL stacks (up to 5 metal layers), line/space resolution down to 2/2μm, polymer dielectric via sizes from 5μm to > 50μm, UBM pad opening and metallization, and full metrology verification including daisy-chain resistance tracking and interlayer alignment measurement.
RDL Process Modules
Copper RDL — Semi-Additive Process (SAP)
Fine-pitch Cu redistribution layer metallization using the semi-additive process. A thin Cu seed layer is sputtered over the polymer dielectric, a thick photoresist mold is patterned with the target RDL trace design, Cu is electroplated into the mold to the target thickness, the photoresist is stripped, and the Cu seed layer is etched back, leaving the isolated Cu RDL traces on the polymer surface. This process achieves finer line/space than subtractive etching and is the industry-standard approach for advanced RDL.
Polymer Dielectrics — PI, BCB, PBO
Three polymer dielectric platforms are available for RDL interlayer and passivation applications. Photosensitive polyimide (PI, HD-8820) — positive-tone, high resolution (2–3μm L/S), excellent thermal stability. Benzocyclobutene (BCB, Cyclotene 3022 series) — negative-tone, ultra-low moisture absorption (< 0.2%), low dielectric constant (εr ≈ 2.65), and excellent planarization. Polybenzoxazole (PBO) — positive-tone, low cure temperature (200–250°C), low stress, and good adhesion for Cu damascene RDL flows.
Multi-Layer RDL Stack
Sequential build-up of multiple Cu RDL layers separated by polymer dielectrics, enabling complex signal routing, power/ground plane integration, and fine-pitch I/O redistribution in fan-out wafer-level packaging. Each layer consists of: polymer coat and pattern (via definition) → Cu seed sputter → photoresist mold → Cu electroplating → resist strip → seed etch → next polymer layer. Multi-layer RDL stacks support up to 5 metal layers with cumulative dielectric thickness of 15–75μm.
UBM Pad & Via Termination
Under-bump metallization (UBM) pad opening and via termination defining the interface between the final RDL Cu layer and solder bump or Cu pillar interconnect. The UBM opening is defined in the top polymer passivation layer (typically 5–10μm thickness), exposing the Cu RDL pad below. A UBM metallization stack (Ti/Cu, TiW/Cu, or electroless Ni/Au) is deposited on the exposed Cu pad to provide solder wetting, diffusion barrier, and adhesion. Pad sizes from 20μm to > 300μm depending on bump pitch.
Process Flow
聚合物塗佈與固化
旋塗聚合物介電質（PI、BCB或PBO）。施加附著促進劑。軟烘烤和最終固化。典型厚度：每層3–10μm。較厚薄膜（10–25μm）可能需要多次塗佈。
通孔光刻
在聚合物介電質中光刻圖案化通孔。光敏聚合物：UV曝光+水性顯影。通孔尺寸5μm至>50μm。顯影後烘烤。O₂電漿除殘膠。
Cu 種子層濺鍍
磁控濺鍍Cu種子層（100–300nm）。先沉積附著層（Ti/TiW，10–30nm）。晶圓傾斜/旋轉以覆蓋通孔側壁。片電阻0.3–1.0 Ω/sq。
光阻模具圖案化
在Cu種子層上塗佈厚正型光阻（3–12μm）。光刻RDL走線模具圖案化。CD量測。除殘膠以清潔溝槽底部。
Cu 電鍍
直流Cu電鍍，10–30 mA/cm²，鍍入光阻模具。目標厚度2–10μm。晶圓均勻性±5%。槽液監測添加劑濃度。
去光阻與種子層蝕刻
光阻去除（溶劑或O₂電漿）。Cu種子層濕蝕刻（H₂SO₄/H₂O₂或HNO₃）。附著層蝕刻。過蝕刻控制<0.5μm/側底切。蝕刻後清洗。
Quality Specifications
| Parameter | Target Specification | Measurement Method |
|---|---|---|
| RDL Line/Space Resolution | 2/2μm (single layer) | SEM top-down, CD-SEM |
| Cu Thickness (within RDL trace) | Target ±5% (1σ) | Profilometry / cross-section SEM |
| Via Chain Resistance | < 1 Ω per 1,000 vias | 4-point resistance on daisy chain |
| Interlayer Alignment | < 2μm (layer-to-layer overlay) | Vernier / box-in-box structures |
| Cu Trace Undercut (seed etch) | < 0.5μm per side | SEM cross-section |
| Polymer Thickness Uniformity | ±5% within-wafer (1σ) | Spectroscopic reflectometry |
| Via Opening CD | Target ±2μm | Optical microscopy / SEM |
| Dielectric Breakdown Voltage | > 100V (for 5μm PI) | DC ramped voltage, adjacent RDL traces |
Specifications apply to single-layer and multi-layer Cu RDL on 200mm silicon or glass substrates. Line/space resolution is polymer-type and thickness dependent. Custom target specifications available.
Semi-Additive Process (SAP) Fundamentals
The semi-additive process differs fundamentally from the subtractive (etch-back) approach used in traditional PCB and wafer-level metallization. In subtractive processing, a blanket metal film is deposited, patterned with photoresist, and etched — which inevitably creates trapezoidal trace cross-sections due to isotropic etching, limits achievable line/space resolution to roughly the metal thickness, and introduces etch-related trace width loss.
In SAP, the sequence is inverted: a thin Cu seed layer is deposited first, a photoresist mold defines where the Cu should be, Cu is electroplated into the mold (not etched away), the resist is stripped, and only the thin seed layer is etched — minimizing etch-induced CD loss. Because electroplated Cu fills the resist mold with near-vertical sidewalls, SAP produces RDL traces with rectangular cross-sections, lower trace resistance for a given width, and line/space resolution limited primarily by photolithography rather than etch isotropy. This is why SAP is the process of record for fine-pitch RDL in advanced packaging.
Multi-Layer RDL Integration
Multi-layer RDL stacks enable complex routing architectures that single layers cannot achieve — power/ground plane distribution (dedicated layers), signal escape routing for high-I/O-count dies, controlled-impedance differential pairs for high-speed signals, and integrated passive components (spiral inductors, MIM capacitors between metal layers).
Each additional RDL layer involves: polymer dielectric coating over the previous Cu layer → via lithography to open connections to the lower Cu layer → Cu seed sputter (with adequate sidewall coverage in high-aspect-ratio vias) → photoresist mold for the next RDL pattern → Cu electroplating → resist strip and seed etch. The interlayer alignment budget (< 2μm) is maintained through optical alignment marks incorporated in each layer's lithography step, referenced to global alignment targets defined on the first layer. Via resistance (< 10 mΩ per via) and daisy-chain continuity (> 99.9% yield on 1,000-via chains) are verified at each layer build-up.
KEY APPLICATIONS
Fan-Out Wafer-Level Packaging (FOWLP)
The primary application of RDL technology. Dies are embedded in mold compound, and RDL layers are built up over the reconstituted wafer to route signals from fine-pitch die pads (40–100μm) to coarse-pitch BGA balls (300–500μm). 1–3 RDL layers are typical for mobile and IoT applications; 3–5 layers for high-density networking and AI accelerators. Multi-die fan-out (chip-first or chip-last) supported for system-in-package (SiP) integration.
Fan-In Wafer-Level Packaging (FIWLP)
Single-layer RDL redistributes peripheral die pads to an area array of solder bumps within the die footprint — no mold compound, no fan-out area. Used for low-I/O-count devices (memory, sensors, power management ICs) where die size accommodates the required bump count. Simpler, thinner, and lower-cost than FOWLP. Typical RDL: 1 layer, 5/5μm L/S, PI or BCB dielectric.
2.5D Interposers
RDL on silicon, glass, or organic interposer substrates provides lateral wiring connecting multiple dies (logic + HBM, chiplets, etc.) mounted side-by-side. 2–4 metal layers with 2/2μm to 5/5μm L/S routing density. Cu RDL with polymer dielectric supports high-speed signaling (28–112 Gbps per lane) with controlled-impedance differential pair routing. TSVs through the interposer provide vertical connections to the package substrate below.
Chiplet Integration
RDL serves as the die-to-die interconnect fabric in chiplet-based architectures, where multiple small dies (compute, memory, I/O, analog) are integrated on a common interposer or fan-out substrate. Ultra-fine-pitch RDL (2/2μm L/S) enables high-density, low-latency connections between chiplets with bump pitches down to 20–40μm. Multi-layer RDL supports the complex routing demanded by heterogeneous chiplet topologies.
Dielectric Material Selection
The choice of polymer dielectric has profound implications for RDL electrical performance, mechanical reliability, and process complexity. Polyimide (PI) offers the highest thermal stability (Tg > 350°C) and broadest process window, making it the default choice for most applications. BCB (benzocyclobutene, Cyclotene 3022 series) provides the lowest dielectric constant (εr ≈ 2.65 vs. 3.3 for PI) and lowest moisture absorption (< 0.2%), reducing both RDL capacitance and moisture-induced reliability risks — critical for high-speed RF and millimeter-wave applications. PBO (polybenzoxazole) offers the lowest cure temperature (200–250°C) and lowest residual stress, preferred for thermally sensitive substrates and ultra-thin packages.
Our engineers help select the optimal dielectric based on your application requirements: operating temperature range, frequency, moisture sensitivity requirements, thermal budget constraints, and target line/space resolution. Mixed-dielectric stacks (e.g., PI for lower layers, BCB for upper layers) are feasible for optimized electrical and mechanical performance.
Seed Layer Etch & Trace Integrity
After Cu electroplating and resist strip, the continuous Cu seed layer short-circuits all RDL traces and must be removed. The seed etch is a critical step — insufficient etch leaves Cu residues causing electrical shorts between adjacent traces; excessive etch causes trace undercut, increasing trace resistance and reducing cross-sectional area. Our H₂SO₄/H₂O₂-based Cu seed etch (alternatively dilute HNO₃ for finer control) is timed for minimum over-etch while ensuring complete seed removal between dense trace arrays. Under-etch verification is performed via electrical isolation testing on interdigitated comb structures (leakage < 1 nA at 5V between adjacent traces). Over-etch (trace undercut) is monitored via SEM cross-section on sacrificial test structures, with a target of < 0.5μm undercut per side.