Polyimide (PI) Processing
Wafer-level polyimide deposition, photolithographic patterning, and thermal curing for MEMS passivation, stress buffer layers, interlayer dielectrics, and redistribution layer applications.
Service Overview
Polyimide (PI) is the workhorse polymer dielectric in MEMS and advanced semiconductor packaging. Its combination of high thermal stability (Tg > 350°C), excellent chemical resistance, low dielectric constant (εr ≈ 3.2–3.5), and mechanical flexibility (elongation up to 60%) makes it the material of choice for stress buffer coatings, interlayer dielectrics, passivation layers, and RDL dielectrics in wafer-level packaging.
GINECHIP offers a complete PI processing service covering both photosensitive polyimides (HD-4100, HD-8820 series — negative and positive tone, aqueous-developable) and non-photosensitive formulations, with all associated steps: surface preparation and adhesion promotion, spin coating to controlled thickness, soft and hard bake curing with programmed thermal profiles, photolithographic patterning (for photo-PI) or dry-etch via definition (for non-photo PI), plasma descum, and final inspection. This end-to-end service ensures optimal film quality, reproducible pattern fidelity, and reliable material integration into your device flow.
Polyimide Materials & Processing Options
Photosensitive Polyimide — HD-4100 Series
Negative-tone, aqueous-developable photosensitive polyimide for thick-film MEMS passivation layers. HD-4100 offers excellent resolution (aspect ratio > 1:1), high thermal stability (Tg > 350°C), low cure temperature option (200°C), and outstanding chemical resistance to common wet etchants and solvents. Widely adopted for stress buffer coatings in wafer-level packaging and interlayer dielectrics in multi-level MEMS structures.
Photosensitive Polyimide — HD-8820 Series
Positive-tone photosensitive polyimide designed for high-resolution patterning with superior mechanical properties. HD-8820 provides finer resolution (2–3μm lines/spaces) compared to negative-tone alternatives, lower moisture absorption (< 0.5%), and excellent adhesion to silicon, SiO₂, Si₃N₄, and common metallizations. Ideal for RDL dielectric layers and fine-pitch via openings.
Non-Photosensitive Polyimide
Thermoplastic and thermoset non-photosensitive PI formulations for applications where lithographic patterning is not required or is achieved via dry etch. These materials offer the widest processing window and highest thermal stability (stable to 500°C). Used for blanket passivation, planarization layers, and applications requiring subsequent dry-etch via definition using O₂/CF₄ plasma with a hard mask.
Adhesion Promotion & Surface Preparation
Proper adhesion promotion is critical for PI-on-substrate reliability. We employ AP3000 or VM-652 organosilane adhesion promoters applied via vapor prime or spin-coat dispense. Substrate dehydration bake (150°C, 5 min) precedes promoter application. For demanding applications on metals (Cu, Al) or after plasma descum, an O₂ plasma activation step enhances surface energy and bonding density.
Process Flow
表面前處理
基板脫水烘烤（150°C，5分鐘，N₂吹掃）。O₂電漿除殘膠以去除有機殘留。氣相或旋塗有機矽烷附著促進劑（AP3000或VM-652）。立即轉入塗佈。
PI 旋塗
動態點膠至晶圓中心。多步旋塗：鋪展（500–1000 rpm）→ 厚度控制（1500–4000 rpm）→ EBR溶劑點膠。目標每層1–50μm。
軟烘烤（預烘烤）
受控熱板/烤箱烘烤以蒸發溶劑而不引發亞胺化。90–120°C、2–5分鐘（光敏PI）或120–150°C、30分鐘（非光敏PI）。升溫速率防止氣泡。
光刻圖案化
UV曝光（i-line，365nm）200–500 mJ/cm²。PEB 50–80°C。TMAH水溶液顯影（0.26N），60–120秒。非光敏PI：硬遮罩+乾蝕刻。
電漿除殘膠與檢測
O₂電漿除殘膠（100–200W，50–100 mTorr，1–2分鐘）。光學顯微鏡檢查圖案保真度和缺陷。關鍵特徵CD量測。
硬烘烤（最終固化）
N₂烤箱中程式化固化。25→200°C（2–3°C/min），保持30分鐘→350–375°C（2–3°C/min），保持60分鐘→冷卻。總共4–6小時。收縮30–50%。FTIR驗證亞胺化>98%。
Quality Specifications
| Parameter | Target Specification | Measurement Method |
|---|---|---|
| Film Thickness Uniformity | ±3% within-wafer (1σ) | Spectroscopic reflectometry / ellipsometry |
| Via Resolution (Photosensitive) | 3–10μm depending on thickness | SEM cross-section / optical microscopy |
| Sidewall Angle | 45–70° (positive tone), 60–85° (negative) | SEM cross-section |
| Surface Roughness (Ra) | < 2nm post-cure | AFM (5μm × 5μm scan) |
| Degree of Imidization | > 98% | FTIR (C=O / C-N stretch ratio) |
| Adhesion | 5B (no delamination) | Cross-hatch tape test (ASTM D3359) |
| Breakdown Voltage | > 250 V/μm | DC ramped voltage, Au dot electrode |
| Residual Stress | < 35 MPa (tensile) after cure | Wafer curvature (Stoney equation) |
Specifications apply to standard PI processing on 100mm–200mm silicon wafers. Values may vary with PI formulation, film thickness, and substrate type. Custom target specifications available upon request.
Curing Profile & Imidization Control
The thermal cure is the most critical step in PI processing, converting the polyamic acid (PAA) precursor into fully imidized polyimide through a cyclodehydration reaction that releases H₂O. Our cure ovens are programmed with controlled ramp rates (typically 2–3°C/min) to prevent bubble formation, ensure complete solvent removal before imidization onset, and minimize residual stress from CTE mismatch between the PI film and silicon substrate.
We monitor degree of imidization via FTIR spectroscopy (tracking the C=O imide carbonyl peak at 1778 cm⁻¹ relative to the C-N stretch at 1378 cm⁻¹), targeting > 98% conversion. Insufficient imidization leads to reduced chemical resistance and poor mechanical properties; over-curing can cause film embrittlement. For applications requiring low-temperature cure (e.g., post-CMOS integration), we offer reduced-temperature cure recipes (200°C–250°C) for HD-4100 with acceptable trade-offs in chemical resistance.
Via Opening & Contact Patterning
For photosensitive polyimides, via openings from 3μm to > 50μm are achieved directly through UV exposure and aqueous development — eliminating the need for a separate photoresist mask and dry-etch step. This reduces process complexity by 2–3 steps compared to non-photosensitive PI patterning. For non-photosensitive PI, vias are defined by depositing a hard mask (SiO₂ or metal), photolithography, and O₂/CF₄ reactive ion etching — offering maximum flexibility in via profile engineering (vertical vs. tapered sidewalls).
After via definition, an O₂ plasma descum step (100–200W, 50–100 mTorr) removes residual PI residue from the via floor to ensure low-contact-resistance electrical connections. Descum uniformity is verified by SEM inspection of test structures on each wafer.
KEY APPLICATIONS
MEMS Passivation
PI is the standard passivation material for MEMS inertial sensors, pressure sensors, microphones, and microfluidic devices. It provides a conformal, chemically resistant barrier that protects silicon microstructures from environmental attack (moisture, ionic contamination) while adding minimal parasitic capacitance due to its low dielectric constant. Typical thickness: 2–10μm.
Stress Buffer Layer
In flip-chip and wafer-level packaging, a PI stress buffer layer (10–20μm thick) decouples CTE mismatch stress between the silicon die (~2.6 ppm/°C) and the organic package substrate (~14–18 ppm/°C), dramatically improving solder joint reliability during thermal cycling. PI's low Young's modulus (3–4 GPa) and high elongation (> 40%) provide effective stress absorption.
RDL Dielectric
In redistribution layer (RDL) processing for fan-out wafer-level packaging, PI serves as both the interlayer dielectric and the final passivation. Multiple PI layers (3–5μm each) are patterned with vias between Cu RDL metal layers, enabling fine-pitch routing from die pads to BGA ball locations. Low moisture absorption (< 0.5%) ensures package reliability under JEDEC moisture sensitivity testing.
Wafer-Level Packaging
PI is extensively used as the dielectric and structural material in wafer-level chip-scale packages (WLCSP). It provides the isolation between silicon and solder bumps (UBM pad opening layer), acts as the solder mask defining bump locations, and serves as the compliant layer absorbing thermomechanical stress during board-level assembly and reliability testing.
Spin Coating Process Control
PI film thickness uniformity is governed by spin speed, dispense volume, solution viscosity, and ambient conditions (temperature, humidity, solvent vapor pressure in the coater bowl). Our spin coaters maintain closed-bowl solvent atmosphere control for consistent drying dynamics and employ automatic edge bead removal (EBR) with solvent dispense to eliminate the thick edge rim that forms during spinning — critical for maintaining uniform lithographic exposure dose across the entire wafer.
For thick PI films (> 20μm), multiple coat-and-bake cycles may be employed to build up total thickness while managing solvent evolution stress. Each sub-layer receives a partial soft bake before the next coat, followed by a single final hard bake for complete imidization of the entire stack. We have qualified multi-coat PI stacks up to 50μm total thickness with no interlayer delamination.
Substrate Compatibility & Adhesion
PI adhesion to the underlying substrate is the single most common failure mode in PI processing. Our surface preparation protocol addresses this through: (1) dehydration bake to remove adsorbed moisture from hydrophilic surfaces (SiO₂, Si₃N₄), (2) organosilane adhesion promoter (AP3000, VM-652) applied as a monolayer via vapor prime for maximum surface coverage, and (3) O₂ plasma activation for difficult-to-bond surfaces such as copper, aluminum, and previously cured PI (multi-layer stacks).
Adhesion is verified per lot using the cross-hatch tape test (ASTM D3359) on witness samples, with a minimum requirement of Classification 5B (0% removal, edges completely smooth). Additional testing — pressure cooker test (PCT, 121°C/100%RH/2 atm) and thermal shock (−65°C to +150°C, 100 cycles) — is available for reliability-critical applications.