teosOxideSilicon.pageTitle

50nm – 10μm teosOxideSilicon.statLabel1

Within-Wafer ±2% teosOxideSilicon.statLabel2

RI 1.46 @ 633nm teosOxideSilicon.statLabel3

Stress < 100 MPa teosOxideSilicon.statLabel4

teosOxideSilicon.sec1Title

teosOxideSilicon.sec1P1

teosOxideSilicon.sec1P2

teosOxideSilicon.calloutText

teosOxideSilicon.sec2Title

teosOxideSilicon.sec2Desc

Low Temp

PECVD TEOS

teosOxideSilicon.methodSubtitlePECVD

Temperature 350–400°C

Deposition Rate 50–200 nm/min

Stress Range -200 to +100 MPa

Conformality Good (> 80%)

Plasma-Enhanced Chemical Vapor Deposition using TEOS precursor at 350–400°C. Plasma energy dissociates the precursor molecules, enabling deposition at significantly lower temperatures than thermal CVD. Produces films with excellent step coverage, conformality, and controllable stress (compressive or tensile). The industry standard for inter-metal dielectrics, passivation layers, and MEMS sacrificial layers where thermal budget constraints preclude high-temperature processing.

High Density

LPCVD TEOS

teosOxideSilicon.methodSubtitleLPCVD

Temperature 700–720°C

Deposition Rate 10–50 nm/min

Stress Range -300 to 0 MPa

Conformality Excellent (> 95%)

Low-Pressure Chemical Vapor Deposition using TEOS at 700–720°C in a hot-wall furnace. Operates in the surface-reaction-limited regime, yielding exceptional within-wafer and wafer-to-wafer uniformity. Produces films with higher density, lower wet etch rates, and superior electrical properties compared to PECVD films. Ideal for hard masks, gate spacers, and applications requiring maximum film quality where thermal budget allows.

teosOxideSilicon.sec3Title

teosOxideSilicon.sec3P1

teosOxideSilicon.sec3P2

teosOxideSilicon.sec4Title

teosOxideSilicon.sec4P1

teosOxideSilicon.sec4P2

teosOxideSilicon.sec5Title

teosOxideSilicon.sec5P1

teosOxideSilicon.sec5P2

teosOxideSilicon.specHeading

teosOxideSilicon.specParam	teosOxideSilicon.specValues
Base Substrate	Prime CZ Si, 100mm–300mm, SSP/DSP, (100) or (111)
Coating Material	SiO₂ via TEOS PECVD
Deposition Method	PECVD (350–400°C), LPCVD TEOS (700–720°C) option
Thickness Range	50nm–10μm, ±5% tolerance
Refractive Index	1.46 ± 0.005 @ 633nm
Within-Wafer Uniformity	±2% for 200mm, ±3% for 300mm
Wafer-to-Wafer Repeatability	±3%
Stress	Compressive or tensile, tunable; < 100 MPa as-deposited
Etch Rate in 6:1 BOE	PECVD: ~20–80 nm/min; LPCVD: ~10–30 nm/min
Dielectric Strength	> 8 MV/cm
Breakdown Voltage	> 400V for 1μm film
Surface Roughness	RMS < 0.5nm
Film Density	2.1–2.2 g/cm³
FTIR Signature	Si-O-Si stretching at 1080 cm⁻¹
Packaging	Vacuum-sealed, single wafer cassette, Class 100 cleanroom

teosOxideSilicon.appHeading

🔬

MEMS Sacrificial Layers

TEOS PECVD oxide is the dominant sacrificial material in surface micromachining. Its high etch rate in HF vapor or BOE relative to thermal oxide and silicon nitride enables precise release of suspended microstructures — accelerometer proof masses, gyroscope combs, pressure sensor diaphragms, and micro-mirror hinges — without attacking structural layers.

🔌

Inter-Metal Dielectrics (IMD)

PECVD TEOS films serve as the primary dielectric between consecutive metal layers in multi-level interconnect stacks. Low deposition temperature preserves underlying aluminum or copper metallization, while excellent gap-fill properties prevent void formation in high-aspect-ratio trenches at sub-micron pitches.

🛡️

Hard Masks for Deep Etching

LPCVD TEOS films provide dense, pinhole-free hard mask layers for deep reactive ion etching (DRIE) of silicon. The low etch rate in fluorine-based chemistries (10–30 nm/min in 6:1 BOE) relative to photoresist enables high-selectivity pattern transfer for through-silicon vias (TSVs) and deep MEMS structures exceeding 300μm depth.

〰️

Optical Waveguides

TEOS SiO₂ films with precisely controlled refractive index (1.46 ± 0.005) and thickness uniformity (±2%) form the core and cladding layers in planar lightwave circuits (PLCs), arrayed waveguide gratings (AWGs), and silicon photonic interposers. Low optical loss and compatibility with CMOS foundry processes make TEOS the material of choice.

🧪

Gate Spacers & Sidewall Passivation

LPCVD TEOS is widely used to form self-aligned gate spacers in CMOS transistor fabrication. The highly conformal deposition coats vertical sidewalls uniformly, defining the lightly-doped drain (LDD) and source/drain implant offset regions critical for short-channel effect control at advanced nodes.

📦

Passivation & Encapsulation

PECVD TEOS oxide combined with silicon nitride forms robust, multi-layer passivation stacks that protect finished ICs from moisture ingress, mobile ion contamination, and mechanical damage. Stress-engineered films prevent die cracking during dicing and packaging while maintaining hermetic sealing.

teosOxideSilicon.metrologyHeading

teosOxideSilicon.metrologyDesc

Spectroscopic Ellipsometry Primary metrology for film thickness and refractive index. Multi-angle (55°, 65°, 75°) measurements at 633nm wavelength across 49-point wafer maps. Thickness accuracy ±0.5nm, refractive index precision ±0.002.

FTIR Spectroscopy Fourier Transform Infrared spectroscopy identifies the characteristic Si-O-Si stretching peak at 1080 cm⁻¹ and Si-OH hydroxyl content at 3400–3650 cm⁻¹. Confirms stoichiometric oxide composition and quantifies hydrogen/water incorporation that affects etch rate and dielectric properties.

Wafer Curvature / Stress Measurement Laser-scanning or interferometric measurement of wafer bow before and after deposition. Stress calculated via Stoney equation; tunable from -300 MPa (compressive) to +100 MPa (tensile) through RF power and pressure adjustments during PECVD.

AFM Surface Roughness Atomic force microscopy over 1×1μm and 10×10μm scan areas. RMS roughness consistently < 0.5nm for both PECVD and LPCVD films, ensuring compatibility with subsequent photolithography and bonding steps.

Wet Etch Rate Calibration Etch rate measured in 6:1 buffered oxide etch (BOE) at 25°C. PECVD: 20–80 nm/min; LPCVD: 10–30 nm/min. Etch rate ratio vs thermal oxide provides a direct proxy for film density and impurity incorporation.

Mercury Probe CV / IV Mercury-probe capacitance-voltage (CV) and current-voltage (IV) measurements on MOS capacitor test structures. Dielectric strength > 8 MV/cm, breakdown voltage > 400V per micron of film thickness.

Optical Emission Spectroscopy (OES) In-situ plasma monitoring during PECVD deposition for real-time process control. Tracks Si, O, and contaminant emission lines to ensure consistent film stoichiometry and detect chamber conditioning drift.

Particle Inspection KLA-Tencor Surfscan surface particle scan at 0.2μm threshold per SEMI M53. Post-deposition particle adders ≤ 5 for Class 100 cleanroom processing.

teosOxideSilicon.ctaHeading

teosOxideSilicon.ctaDesc

teosOxideSilicon.ctaBtn teosOxideSilicon.ctaShopBtn teosOxideSilicon.ctaContactBtn

teosOxideSilicon.ctaMeta1 teosOxideSilicon.ctaMeta2 teosOxideSilicon.ctaMeta3 teosOxideSilicon.ctaMeta4

teosOxideSilicon.heroTitle