CoPoS — Chip-on-Panel-on-Substrate
Panel-level packaging that replaces traditional round silicon interposers with square glass panels, achieving 95%+ area utilization and 4.5× the output of 12-inch wafers.
概要
CoPoS (Chip-on-Panel-on-Substrate) represents the next paradigm shift in advanced packaging, moving from round 300mm silicon interposers to large square glass panels. By replacing the circular silicon interposer with a 510×515mm glass panel, CoPoS dramatically increases the number of dies that can be integrated per substrate, pushing area utilization from ~70% on wafer to 95%+ on panel, and delivering a 4.5× increase in unit output per carrier.
This panel-level approach is the critical path for AI chips to break through the 9× reticle size limit and integrate more HBM stacks. As AI accelerators continue to grow in die size and memory bandwidth requirements, CoPoS enables the next generation of ultra-large interposers that wafer-level packaging simply cannot accommodate.
Key Technology Features
Panel-Level Scaling
510×515mm glass panels replace 300mm silicon wafers, delivering 4.5× more area per carrier. Square format eliminates the edge-loss inefficiency inherent to circular wafer processing, enabling true high-volume manufacturing economics for advanced packages.
Glass Core Substrate
Glass offers superior dimensional stability (CTE 3–8 ppm/K, tunable), near-zero dielectric loss (<0.005 @ 10GHz), and atomic-level surface smoothness. These properties make glass the ideal substrate for high-speed, high-density interconnects required by AI/ML chips.
TGV (Through-Glass Via) Metallization
Through-glass vias with 20–50μm diameter and aspect ratios up to 6:1 provide the vertical electrical connections between RDL layers. Copper-filled TGVs achieve low resistance and high reliability, replacing traditional TSV approaches in the interposer.
Multi-Layer RDL Integration
Fine-pitch redistribution layers (L/S down to 0.4/0.4μm) are built on the glass panel using copper damascene processes. Multiple RDL layers enable complex die-to-die routing for HBM, GPU, and I/O chiplet integration on a single panel.
GINECHIP Solutions
Full range of panel-grade glass substrates including Borofloat 33, fused silica/quartz, and single-crystal quartz, available in custom panel sizes up to 510×515mm.
High-quality silicon wafers for RDL seed layer deposition, with precise thickness control and surface roughness <0.5nm RMS for optimal copper adhesion.
Material supply and process consulting for through-glass via formation and metallization, including barrier/seed layer deposition and copper electroplating chemistries.
CMP polishing, thin-film deposition, and photolithography services adapted for panel formats, leveraging our expertise in large-format substrate processing.
Target Applications
CoPoS is designed for AI/ML accelerators, high-performance computing (HPC) processors, and next-generation networking chips that require ultra-large interposers beyond 9× reticle size. The technology is also being adopted for advanced 2.5D packages integrating multiple HBM stacks with large logic dies, where the panel format provides a natural advantage in throughput and cost.