平坦度再認証
包括的なウェーハ平坦度測定と再認証。
概要
Wafer flatness is not a single number — it is a multi-dimensional quality attribute that governs lithographic pattern fidelity, CMP uniformity, bonding yield, and wafer handling reliability. As semiconductor design rules shrink and stepper numerical apertures increase, the depth of focus (DOF) available for lithographic imaging decreases proportionally — driving ever-tighter flatness specifications. A wafer that is "flat enough" for a 248nm lithography process may be completely unacceptable for 193nm immersion or EUV patterning.
GINECHIP's flatness re-certification service provides comprehensive, NIST-traceable measurement and documentation of all standard flatness parameters using high-density capacitance gauge scanning. Whether you need to re-certify reclaimed wafers before return to your fab, qualify incoming substrates against lithography tool requirements, or trend flatness evolution across multiple reclaim cycles — our metrology delivers the accuracy, resolution, and documentation your process engineers need.
平坦度測定サービス
TTV — Total Thickness Variation
TTV measures the difference between the maximum and minimum thickness values across the entire wafer. It is the most fundamental global flatness metric and directly impacts lithography depth-of-focus budget, CMP uniformity, and wafer handling in automated tools. TTV re-certification provides a verified TTV value with full wafer thickness map showing the spatial distribution of thickness variation across the wafer surface.
STIR — Site Total Indicator Reading
STIR quantifies the total thickness variation within a defined site area on the wafer surface. Each site corresponds to a single exposure field of the lithography stepper (typically 26mm × 33mm for 300mm wafers). STIR is the critical metric for lithography qualification: the site-level flatness must be within the stepper depth of focus to ensure pattern fidelity across the entire exposure field.
SFQR — Site Front least sQuares Range
SFQR is similar to STIR but removes the best-fit plane from each site measurement, effectively decoupling site-level flatness from global wafer shape (bow and warp). SFQR is the preferred metric for modern high-NA lithography tools that can compensate for tilt within each exposure field, representing a more accurate measure of the flatness quality that actually impacts focus uniformity during exposure.
GBIR — Global Backside Ideal Range
GBIR measures the wafer thickness variation relative to an ideal, flat backside reference plane. This metric is critical for processes where the wafer is chucked flat against a reference surface — such as lithography exposure, plasma etching on electrostatic chucks, and CMP polishing. GBIR re-certification confirms that the wafer backside can be reliably flattened by the process tool chuck.
プロセスフロー — 再認証シーケンス
ウェーハ登録
各ウェーハをロットIDと仕様で登録。
環境調整
ウェーハを計測ラボで23±0.5°Cに調整。
高密度グリッドスキャン
300mmウェーハを≥2,500ポイントでスキャン。
パラメータ計算
TTV/STIR/SFQR/GBIRを計算し統計分析。
SEMI分類
測定平坦度に基づきSEMI M1-M13分類を割り当て。
レポート生成
厚さマップとデータエクスポート付き完全分析証明書。
品質仕様 — 計測システム
| パラメータ | 目標仕様 | 測定方法 |
|---|---|---|
| TTV Measurement Accuracy | ± 0.2μm (k=2) | NIST-traceable thickness standards |
| TTV Repeatability | ± 0.1μm (3σ) | Repeat measurements on standard wafer |
| Point Density (200mm) | ≥ 1,000 points | Capacitance gauge grid scan |
| Point Density (300mm) | ≥ 2,500 points | Capacitance gauge grid scan |
| Site Size Accuracy | ± 0.5mm in X and Y | Laser interferometer stage calibration |
| Environmental Control | 23 ± 0.5°C, 45 ± 5% RH | NIST-traceable sensors |
| Data Traceability | NIST/SEMI chain of calibration | Calibration certificates on file |
| Report Turnaround | 24–48 hours standard | LIMS automated processing |
NISTトレーサブル校正標準で検証。
測定方法 — 静電容量計 vs 干渉計
静電容量計方式
Our primary flatness measurement system uses dual-capacitance-gauge scanning, which measures the wafer thickness directly by placing the wafer between two precisely aligned capacitance probes. This method is intrinsically insensitive to wafer bow and warp because it measures the physical separation between the two probes with the wafer present, compared to their separation without the wafer. Capacitance gauges achieve sub-nanometer resolution and are the industry-preferred method for TTV, STIR, SFQR, and GBIR measurements per SEMI MF1530. The non-contact nature eliminates surface damage risk, and the high-speed scanning enables > 2,500 measurement points per 300mm wafer in under 30 seconds.
干渉計（光学）方式
Optical interferometry provides a complementary measurement capability, measuring the wafer surface topography by analyzing the interference pattern of light reflected from the wafer surface and a reference flat. This method excels at full-field surface mapping with sub-nanometer vertical resolution and is particularly useful for visualizing surface features such as nanotopography, polishing marks, and localized thickness anomalies. Interferometry is preferred when surface topography information is required in addition to thickness, or when the wafer material is non-conductive (e.g., glass, sapphire) and cannot be measured by capacitance gauge. We use both methods to cross-validate measurements on critical lots.
リソグラフィ認定 — ノード別平坦度要件
Wafer flatness directly determines the usable depth of focus (DOF) for lithographic exposure. The relationship is straightforward: if the site-level flatness (SFQR or STIR) exceeds the stepper's available DOF, portions of the exposure field will be out of focus, resulting in degraded CD uniformity, pattern bridging, or missing features — particularly at the edges of each exposure field.
技術ノード別平坦度要件
For mature nodes (≥ 180nm, i-line or 248nm lithography), DOF typically exceeds 500nm, and STIR specifications of ≤ 0.5μm are generally adequate. For advanced nodes (90nm–28nm, 193nm dry/immersion lithography), DOF shrinks to 200–400nm, driving STIR/SFQR requirements to ≤ 0.15–0.25μm. For leading-edge nodes (≤ 14nm, 193nm immersion with multi-patterning, EUV), DOF is below 100nm, and site-level flatness specifications of ≤ 0.05μm are required — making flatness re-certification an essential incoming quality control step before committing high-value wafers to the lithography process.
SEMI平坦度分類
SEMI standards M1 through M13 define a comprehensive classification system for silicon wafer flatness. Our re-certification reports assign the appropriate SEMI classification based on measured data, enabling direct comparison with wafer supplier specifications. Key classifications include: SEMI M1 (silicon wafer dimensional specifications by diameter), SEMI M11 (flatness classifications for polished wafers), SEMI M12 (flatness classifications for epitaxial wafers), and SEMI M13 (flatness classifications for SOI wafers). Each classification defines threshold values for TTV, STIR, SFQR, GBIR, and other parameters by wafer diameter and application grade (Prime, Test, Monitor, Reclaim).
再認証レポート内容
Every lot processed through our flatness re-certification service receives a comprehensive Certificate of Analysis including: (1) Wafer identification data (lot ID, wafer ID, diameter, material, orientation, dopant type); (2) Raw thickness data matrix and color-coded thickness map for each wafer; (3) Calculated flatness parameters (TTV, STIR, SFQR, GBIR) with statistical summaries; (4) Site-level flatness map with stepper field overlay; (5) SEMI classification assignment; (6) Pass/fail determination against customer-specified limits; (7) Measurement system traceability data (instrument serial number, calibration date, NIST standard reference); (8) Environmental conditions during measurement (temperature, humidity). Reports are provided in PDF format with CSV raw data export for customer SPC database integration.
アプリケーション
再生ウェーハ再認定
After wafer reclaim processing, flatness must be re-verified before the wafers can be accepted back into the fab. Each reclaim cycle removes material (typically 2–5μm for standard reclaim, more for aggressive strip processes), which can alter the wafer's flatness signature. Re-certification provides the incoming quality gate that ensures reclaimed wafers meet the same flatness specifications as new test/monitor wafers — and identifies any wafers that have accumulated unacceptable flatness degradation across reclaim cycles.
サプライヤー品質監査
Independent third-party flatness verification provides an objective quality audit of your wafer supplier. Supplier certificates of conformance are based on the supplier's own metrology — which may differ from your in-house measurement due to tool-to-tool variation, environmental differences, or measurement methodology. Our NIST-traceable re-certification eliminates these discrepancies and provides an independent flatness baseline for supplier quality management and incoming material disposition.
品質保証
Our capacitance gauge metrology system undergoes daily calibration verification against NIST-traceable thickness standards. Measurement repeatability is characterized through continuous SPC monitoring of standard reference wafers, with control charts maintained for TTV, STIR, and SFQR accuracy. The metrology laboratory environment is maintained at 23 ± 0.5°C and 45 ± 5% RH, with continuous temperature and humidity logging for complete measurement traceability. All measurement data is archived in our LIMS for a minimum of 5 years, enabling long-term flatness trending and historical comparison.