RDLバンプウェーハ — 再配線層とウェーハレベルサービス | GINECHIP

0.4–5μm L/SStat Rdl Rules

1–8 LayersStat Stack Height

10–500μmStat Bump Pitch

200mm, 300mmStat Wafer Diam

概要

当社の能力とサービスの包括的な概要

業界トップクラスの品質と精度を提供します

RDL技術レベル

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L/S: 5/5μmCu thickness: 5–8μmVia: 20–30μm diaPI dielectric: 5–8μm thickLayers: 1–3Bump pitch: 300–500μm

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L/S: 2/2μmCu thickness: 3–5μmVia: 10–15μm diaBCB or advanced PI dielectricLayers: 2–5Bump pitch: 130–300μm

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L/S: 0.4/0.4μmCu thickness: 1–3μmVia: 5–10μm diaSiO₂ dielectric (CVD)Layers: 2–8Damascene Cu + TaN/Ta barrier

バンプ技術オプション

Wafer bumping creates interconnect structures on semiconductor wafers for flip-chip assembly. Our comprehensive bumping platform supports multiple materials, pitches, and aspect ratios across 100mm to 300mm wafers.

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Alloys: SAC305, SAC405, SnPbPitch: 130–400μmHeight: 50–100μmUBM: Ti/Cu or TiW/CuReflow: wafer-level

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Pillar height: 20–80μmSolder cap: 10–25μm SnAgPitch: 40–130μmNi barrier optionAR: 2:1–5:1

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Pitch: 10–55μmDiameter: 5–25μmCu/Ni/SnAg stackHybrid bonding compatibleMass reflow or TCB

接合プロセスフロー

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主要アプリケーション

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集積受動部品

Integrated Passive Devices fabricated in the RDL layers provide capacitors, inductors, and resistors directly on the wafer surface. IPD integration reduces component count, minimizes parasitics, and improves electrical performance for RF and power management applications.

品質保証と計測

当社の品質マネジメントシステムはISO 9001:2015認証を取得し、SEMI標準、RoHS、REACH、紛争鉱物規制に準拠しています。各出荷にはロットトレーサビリティ付きの適合証明書が含まれます

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