CoWoS — Chip-on-Wafer-on-Substrate
The industry-standard 2.5D packaging platform for AI GPUs, integrating logic and HBM on a silicon interposer with high-density interconnects for maximum compute performance.
Обзор
CoWoS (Chip-on-Wafer-on-Substrate) is TSMC's flagship 2.5D advanced packaging technology that has become the de facto standard for AI and HPC processors. It uses a large silicon interposer (up to 3× reticle size) as the interconnect fabric between logic dies (GPU/CPU) and high-bandwidth memory (HBM) stacks. The interposer provides dense, fine-pitch wiring that far exceeds what is possible with organic substrates, enabling the massive data throughput required by modern AI accelerators.
TSMC's CoWoS capacity demand is projected to surge from 1.38 million wafers in 2026 to 2.68 million wafers in 2027, driven by insatiable AI chip demand. This explosive growth creates opportunities across the supply chain for silicon interposer wafers, TSV processing, and RDL metallization materials — all areas where GINECHIP provides critical support to the ecosystem.
Key Technology Features
Silicon Interposer Technology
A passive silicon interposer (300mm, ~100μm thick) provides the high-density wiring layer between logic and memory. The interposer features through-silicon vias (TSVs) for vertical connection to the package substrate, and multi-layer RDL for horizontal die-to-die routing.
TSV (Through-Silicon Via)
TSVs with diameters as small as 10μm and aspect ratios of 10:1 provide the vertical electrical pathways through the silicon interposer. The TSV middle (via-middle) process integrates vias after FEOL but before BEOL metallization, balancing performance with manufacturing complexity.
Fine-Pitch RDL (Redistribution Layer)
Multi-layer copper RDL with line/space of 0.4/0.4μm enables dense die-to-die interconnects. Copper damascene processing ensures high yield and reliability for the fine-pitch wiring needed to connect hundreds of signals between GPU and HBM dies.
C4 & μ-Bump Metallization
Controlled Collapse Chip Connection (C4) bumps on the interposer bottom and micro-bumps (μ-bump) on the top connect the interposer to the package substrate and the logic/memory dies respectively. GINECHIP provides the UBM materials and wafer bumping services for these critical interconnects.
GINECHIP Solutions
300mm silicon wafers with thickness down to 100μm, ultra-flat surfaces (TTV <1μm), and precise resistivity control for CoWoS interposer fabrication.
Full TSV process support including deep silicon etching (Bosch process), sidewall passivation, barrier/seed layer deposition, and copper electroplating for vias down to 10μm diameter.
Copper damascene processing for fine-pitch RDL with L/S down to 0.4/0.4μm, including CMP planarization to ensure flatness for subsequent layer stacking.
Under-bump metallization (UBM) and bumping services for C4 and μ-bump fabrication, including Ti/Cu, Ti/Ni/Au, and ENIG surface finishes.
Target Applications
CoWoS is the primary packaging platform for NVIDIA H100/H200/B200 GPUs, AMD MI300X accelerators, Intel Gaudi AI processors, and custom ASICs from Google (TPU), Amazon (Trainium), and Microsoft. The technology also supports HPC CPUs, networking switch ASICs, and FPGA-based accelerators that require high-bandwidth memory integration.
Power Your CoWoS Supply Chain
From silicon interposer wafers to TSV, RDL, and bumping services, GINECHIP is your partner for the materials and processing that drive CoWoS production.